Module axi_mux

Parameters

`SlvAxiIDWidth`

`slv_aw_chan_t`

`mst_aw_chan_t`

`w_chan_t`

`slv_b_chan_t`

`mst_b_chan_t`

`slv_ar_chan_t`

`mst_ar_chan_t`

`slv_r_chan_t`

`mst_r_chan_t`

`slv_req_t`

`slv_resp_t`

`mst_req_t`

`mst_resp_t`

`NoSlvPorts`

`MaxWTrans`

`FallThrough`

`SpillAw`

`SpillW`

`SpillB`

`SpillAr`

`SpillR`

`MstIdxBits`

`MstAxiIDWidth`

Ports

`clk_i`

`rst_ni`

`test_i`

`slv_reqs_i`

`slv_resps_o`

`mst_req_o`

`mst_resp_i`

Types

Signals

`mst_aw_chan: mst_aw_chan_t`

`w_fifo_data: switch_id_t`

`mst_w_chan: w_chan_t`

`switch_b_id: switch_id_t`

`mst_b_chan: mst_b_chan_t`

`mst_ar_chan: mst_ar_chan_t`

`switch_r_id: switch_id_t`

`mst_r_chan: mst_r_chan_t`