library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use WORK.BASIC.all;

-- Ok this will hopefully be the systolic adder :-)
-- I'll use a lot of variables hope this will do 

entity syst_adder is
port (
      a,b,c,d : in  std_logic_vector(9 downto 0);
      sum     : out std_logic_vector(12 downto 0)
     );
end syst_adder;

architecture behaviour of syst_adder is
signal qs : UNSIGNED(8 downto 0);

begin
 process (a,b,c,d,qs)
      variable L1a,L1b,L1i  : std_logic_vector(8 downto 0);
      variable L1s,L1c      : std_logic_vector(8 downto 0);
      variable ssum         : std_logic_vector(3 downto 0); 
  begin  


      -- first level inputs

      for I in 0 to 8 loop
        L1a(I) := a(I+1);
        L1b(I) := b(I);
      end loop;
      ssum(0) := a(0); 

      -- call the HA_stack
     
      HA(L1a,L1b,L1s,L1c);

      for I in 0 to 7 loop
        L1a(I) :=  c(I);
        L1b(I) :=  L1s(I+1);
        L1i(I) :=  L1c(I);
      end loop;
      L1a(8) := c(8);
      L1b(8) := b(9);
      L1i(8) := L1c(8);
      ssum(1) := L1s(0);

      -- call the FA_stack
      FA(L1a,L1b,L1i,L1s,L1c);

      for I in 0 to 7 loop
        L1a(I) :=  d(I);
        L1b(I) :=  L1s(I+1);
        L1i(I) :=  L1c(I);
      end loop;
      L1a(8) := d(8);
      L1b(8) := c(9);
      L1i(8) := L1c(8);
      ssum(2) := L1s(0);
      -- call the FA_stack
      FA(L1a,L1b,L1i,L1s,L1c);

      -- the final line up 
      for I in 0 to 7 loop
        L1a(I) := L1s(I+1);
        L1b(I) := L1c(I);
      end loop; 

      L1a(8) := d(9);
      L1b(8) := L1c(8);
      ssum(3) := L1s(0);

      -- now add this as fast as possible
      -- try to adapt a CLA; 
      
      -- this is strange actually I'll have to convert to
      -- signed numbers... 
      
      qs <= UNSIGNED(L1a) + UNSIGNED(L1b);
      sum(12 downto 4) <= STD_LOGIC_VECTOR(qs); 
      
      sum(3 downto 0) <= ssum;
      
  end process;
end behaviour;