Aries: An LSI Macro-Block for DSP Applications

[PREV] [TOC]

Bibliography

  1. M. A. Bayoumi and E. E. Swartzlander, "VLSI Signal processing Technology," Kluwer Academic Publishers, 1994.

  2. L. E. Thon, "Low-Power Digital Disk-Drive Electronics," In Arcitectural and Circuit design for Portable Electronic Systems , Lausanne, 1997.

  3. Y. Leblebici, A. Kepkep, F. K. Gürkaynak, H. Özdemir, and U. Çilingiroğlu, "A Fully Pipelined Programmable Image Filter Architecture Based on Capacitive Threshold-Logic," accepted for publication on IEEE Trans. on VLSI Sytems.

  4. C. Piguet, "Ultra Low-Power Digital Design," in CMOS \& BiCMOS IC Design'97 , Lausanne, 1997.

  5. R. Zimmermann, "Computer Arithmetic: Principles, Architectures, and VLSI Design," Lecture notes, Integrated Systems Laboratory, ETH Zürich, 1997.

  6. T.H. Meng, "Between ASICS and MMX: The Window for MediaProcessors," In Arcitectural and Circuit design for Portable Electronic Systems, Lausanne, 1997.

  7. Y. Leblebici, A. Kepkep, F. K. Gürkaynak, H.Özdemir, and U. Çilingiroğlu, "Fully Programmable Real Time (3x3) Image Filter Based on Capacitive Threshold-Logic Gates," In Proc. of IEEE International Symposium on Circuits and Systems 1997, pp 2072-2075, 1997.

  8. H. Özdemir, A. Kepkep, B. Pamir, Y. Leblebici, and U. Çilingiroğlu, "A Capacitive Threshold-Logic Gate," IEEE Journal of Solid State Circuits , vol SC-31, pp.1141-1149, August, 1996.

  9. Y. Leblebici, H. Özdemir, A. Kepkep, and U.Çilingiroğlu, "A Compact (8x8)-Bit Serial/Parallel Multiplier Based on Capacitive Threshold Logic," Proc. 1995 European Conference on Circuit Theory and Design , pp. 55-58, August, 1995.

  10. Y. Leblebici, H. Özdemir, A. Kepkep, and U. Çilingiroğlu, "A Compact Parallel (31,5)-Counter Circuit Based on Capacitive Threshold-Logic Gates", IEEE Journal of Solid State Circuits , vol SC-31, pp.1177-1183, August, 1996.

  11. Y. Leblebici, F. K. Gürkaynak, and D. Mlynek, "A Compact 31-Input Programmable Majority Gate Based on Capacitive Threshold Logic," accepted for presentation at the 1998 IEEE International Symposium on Circuits and Systems.

  12. T. Huisman, "Counters and Multipliers with Threshold Logic," Master's Thesis, Laboratory of Computer Architecture and Digital Techniques (CARDIT) , Faculty of Electrical Engineering, Delft University of Technology, 1-68340-28(1995)08, May, 1995.

  13. E.E. Swartzlander, "Parallel Counters," IEEE Trans. Computers , vol. C-22, pp 1021-1024, September, 1973.

  14. L. Dadda, "Some Schemes for Parallel Multipliers," Alta Frequenza , vol 34, pp. 349-356, May, 1965.

  15. R. Minnick, "Linear Input Logic", IRE Trans. on Electronic Computers , vol:EC-10,pp. 6-16, March, 1961.

  16. W. H. Kautz, "The Realization of Symmetric Switching Functions with Linear Input Logical Elements," IRE trans. on Electronic Computers , vol:EC-10, pp. 371-378, September, 1961.

  17. C.I. Göknar, Personal Correpondance.

  18. J. Yuan and C. Svensson, "High Speed CMOS Circuit Technique", IEEE Journal of Solid State Circuits , vol SC-24, pp.62-70, 1989.

  19. S. M. Kang, and Y. Leblebici , "CMOS Digital Integrated Circuits, Analysis and Design", McGraw-Hill , 1996.

  20. B. Aksoy, "0.8um-CMOS AMS Teknolojisinde ASIC İşlem Blokları (Functional ASIC Blocks for the 0.8-um CMOS AMS Technology)", Final Project , Faculty of Electrical and Electronics Engineering, Istanbul Technical University, June 1997.

  21. N.H.E. Weste and K. Eshraghian, "Principles of CMOS VLSI Design," Addison Wesley , 1993.

  22. R. Zimmermann and W. Fichtner, "Low-Power Logic Styles: CMOS Versus PASS-Transistor Logic," IEEE Journal of Solid State Circuits , vol SC-32, pp.1079-1090, July, 1997.

  23. A. P. Chandrakasan and R. W. Brodersen, "Low Power Digital CMOS Design", Kluwer Academic Publishers , 1995.

  24. J. M. Rabaey, "Digital Integrated Circuits, A Design Perspective," Prentice-Hall , 1996.

  25. H. -J. Pfleiderer, "Systolic Arrays," in Advanced Digital IC Design, Lausanne, 1997.

  26. J. M. Wang, S.-C. Fang, and W.-S. Feng, "New efficient Designs for XOR and XNOR Functions on the Transistor Level," IEEE Journal of Solid State Circuits, vol SC-29, pp.780-786, July, 1994.

[PREV] [TOC] [TOP]

These pages by KGF
22.1.1998