library IEEE;
use IEEE.std_logic_1164.all;

entity tb_systolic is
end tb_systolic;

architecture TESTBENCH of tb_systolic is

  signal  a,b,c,d: STD_LOGIC_VECTOR (9 downto 0);
  signal  sum:     STD_LOGIC_VECTOR (12 downto 0);
  
  component syst_adder port (a,b,c,d: in  STD_LOGIC_VECTOR( 9 downto 0);
                           sum    : out STD_LOGIC_VECTOR(12 downto 0) );
  end component;

begin
    UUT: syst_adder
            port map(a,b,c,d,sum);
    
    process
      begin
        a <= "0000000000" after 0 ns, 
             "0000000000" after 10 ns, 
             "0000000001" after 20 ns,
             "0000000000" after 30 ns,
             "0000000001" after 40 ns,
             "0000000100" after 50 ns; 
             
        b <= "0000000000" after 0 ns, 
             "0000000001" after 10 ns, 
             "0001100000" after 20 ns,
             "0000000010" after 30 ns,
             "0000000001" after 40 ns,
             "0000000011" after 50 ns;
             
        c <= "0000000000" after 0 ns, 
             "0000000010" after 10 ns, 
             "1100110011" after 20 ns,
             "0000000000" after 30 ns,
             "0000000001" after 40 ns,
             "0000000000" after 50 ns; 
             
        d <= "0000000000" after 0 ns, 
             "0000000100" after 10 ns, 
             "0111100110" after 20 ns,
             "0000000000" after 30 ns,
             "0000000001" after 40 ns,
             "0000000000" after 50 ns;
      wait for 60 ns;
    end process; 
end TESTBENCH;

configuration cfg_tb_systolic of tb_systolic is
  for TESTBENCH
    for UUT: syst_adder
    end for;
  end for;
end;