Preface

Summary

1.Introduction

• 2.1.Binary Number Systems
  • 2.1.1.Binary Number Systems
  • 2.1.2.Gray Numbers
  • 2.1.3.Redundant Number Systems
  • 2.1.4.Floating-Point Number Systems
• 2.2.Hardware Solutions
• 2.3.Dedicated Hardware versus Generic Processors

• 3.1.Capacitive Threshold Logic
  • 3.1.1.CTL Operation Principle
  • 3.1.2.CTL-Based Parallel Counter
• 3.2.Description of the Architecture
• 3.3.Realization of the Image Filter Chip
• 3.4.Design Problems Associated with the Taurus Architecture

• 4.1.Description of the General Architecture
• 4.2.Pipeline Structure and Pipeline Elements of Aries

• 5.1.Practical Semiconductor Storage Methods
• 5.2.General SRAM Structure
• 5.3.Basic SRAM Cell
• 5.4.Dual Port SRAM Cell
• 5.5.Pre-charge Circuit
• 5.6.Sense-Amplifier
• 5.7.Write-circuit
• 5.8.Row Decoders
• 5.9.Control Circuitry
• 5.10.Layouts of RAM Blocks

• 6.1.Systolic Adder
  • 6.1.1. 1-Bit Full Adder
  • 6.1.2.Ripple Carry Adder
  • 6.1.3.Parallel Prefix Adders
  • 6.1.4.Negative Numbers
  • 6.1.5.Design of the Systolic Adder
• 6.2.Accumulator
• 6.3.Output stage
• 6.4.Final Adder

• 7.1.Final Layout
• 7.2.Operation of Aries
  • 7.2.1.Initialization Mode
  • 7.2.2.Computation Mode
• 7.3.Implementation

• 8.1.Overview of Design Methodologies
• 8.2.Full Custom Design Methodology
  • 8.2.1.Signal Flow
  • 8.2.2.Design Rules
  • 8.2.3.Common Pitfalls
  • 8.2.4.Schematic Level Enhancements for Efficient Layouts
• 8.3.Case Study: Design of the Systolic Adder
  • 8.3.1.Functional Verification
  • 8.3.2.Design of the Full Adder
    • 8.3.2.1.Schematics
    • 8.3.2.2.Layout of the Full Adder Cell
  • 8.3.3.Design of CPA Section
    • 8.3.3.1.Preprocessing Stage
    • 8.3.3.2.The Delta Cell
    • 8.3.3.3.The Postprocessing Cell
  • 8.3.4.Coping With Negative Numbers
  • 8.3.5.Comparison with HDL

Results

Bibliography