The following two chips were fabricated for two student semester thesis. They implement two AES finalist algorithms, Rijndael and Serpent. Both designs can encrypt and decrypt at 2 Gbit/s ECB modus, occupy 49 sqmm silicon area (one corner is 7 mm in both cases) in 0.6 um AMS technology and consist of roughly 300,000 transistors. They work at around 100 MHz, and have been both tested.
Hans-Peter Mathys made both pictures using micro spots, and I think they look gorgeous. click on the pictures for larger versions (roughly 1000 x 1000). The originals are 5000x5000, mail me for a copy.
KGF
27 Dec 2002