#!/bin/sh ############################################################ ## Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich ## http://www.iis.ee.ethz.ch/~sha3 ############################################################ # sample script to run gatelevel simulation with sdf timings # # >>> Adapt it for your design !!! <<< (see README.postlayout) # vsim-6.5a -t 1ps -lib gate \ -L fsd0a_a_generic_core_verilog -L fod0a_b25_t25_generic_io_verilog \ -sdftyp MutInst=../encounter/out/blake_small2.sdf.gz +sdf_verbose \ -do "run 252.8 ns; vcd file ../modelsim/vcd/blake_small2.vcd; vcd add -r /blakeTb/MutInst/*; run 4977 ns; quit -f" \ -v2k_int_delays +no_glitch_msg\ blakeTb # use: # # vsim-6.5a -help # # to see available options # -do "run 103.35 ns; vcd file ../modelsim/vcd/blake_small.vcd; vcd add -r /blakeTb/MutInst/*; run 5042.25 ns; quit -f" \