------------------------------------------------------------
-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use work.blakePkg.all;

entity blake is
  port (
    CLKxCI   : in  std_logic;
    RSTxRBI  : in  std_logic;
    MxDI     : in  std_logic_vector(WWIDTH*16-1 downto 0);
    TxDI     : in  std_logic_vector(WWIDTH*2-1 downto 0);
    HxDO     : out std_logic_vector(WWIDTH*8-1 downto 0);
    InENxSI  : in  std_logic;
    OutENxSO : out std_logic
    );

end blake;

architecture hash of blake is

  component controller
    port (
      CLKxCI      : in  std_logic;
      RSTxRBI     : in  std_logic;
      VALIDINxSI  : in  std_logic;
      VALIDOUTxSO : out std_logic;
      ICNTxSO     : out unsigned(3 downto 0);
      ROUNDxSO    : out unsigned(3 downto 0);
      NewChainxSO : out std_logic;
      UseIVxSO    : out std_logic
      );
  end component;

  component roundreg
    port (
      CLKxCI   : in  std_logic;
      RSTxRBI  : in  std_logic;
      WEIxSI   : in  std_logic;
      ICNTxSI  : in  unsigned(3 downto 0);
      ROUNDxSI : in  unsigned(3 downto 0);
      VxDI     : in  SUB16;
      MxDI     : in  SUB16;
      VxDO     : out SUB16
      );
  end component;

  signal VxD, VFxD, MxDN, MxDP : SUB16;
  signal HxDN, HxDP            : SUB8;
  signal TxD                   : SUB2;
  signal ICNTxS, ROUNDxS       : unsigned(3 downto 0);
  signal NewChainxS, UseIVxS   : std_logic;

-------------------------------------------------------------------------------
-- BEGIN **********************************************************************
-------------------------------------------------------------------------------
begin  -- hash

  p_un16 : for i in 15 downto 0 generate
    MxDN(15-i) <= MxDI(WWIDTH*(i+1)-1 downto WWIDTH*i) when InENxSI = '1' else MxDP(15-i);
  end generate p_un16;

  p_un8: for i in 7 downto 0 generate
    HxDO(WWIDTH*(i+1)-1 downto WWIDTH*i) <= HxDN(7-i);
  end generate p_un8;

  p_un2: for i in 1 downto 0 generate
    TxD(1-i) <= TxDI(WWIDTH*(i+1)-1 downto WWIDTH*i);
  end generate p_un2;
  
  -----------------------------------------------------------------------------
  -- CONTROLLER
  -----------------------------------------------------------------------------
  u_controller: controller
    port map (
      CLKxCI      => CLKxCI,
      RSTxRBI     => RSTxRBI,
      VALIDINxSI  => InENxSI,
      VALIDOUTxSO => OutENxSO,
      ICNTxSO     => ICNTxS,
      ROUNDxSO    => ROUNDxS,
      NewChainxSO => NewChainxS,
      UseIVxSO    => UseIVxS
      );
  
  -----------------------------------------------------------------------------
  -- INITIALIZATION
  -----------------------------------------------------------------------------
  VxD(0)  <= HxDN(0) when UseIVxS = '0' else IV(0);
  VxD(1)  <= HxDN(1) when UseIVxS = '0' else IV(1);
  VxD(2)  <= HxDN(2) when UseIVxS = '0' else IV(2);
  VxD(3)  <= HxDN(3) when UseIVxS = '0' else IV(3);
  VxD(4)  <= HxDN(4) when UseIVxS = '0' else IV(4);
  VxD(5)  <= HxDN(5) when UseIVxS = '0' else IV(5);
  VxD(6)  <= HxDN(6) when UseIVxS = '0' else IV(6);
  VxD(7)  <= HxDN(7) when UseIVxS = '0' else IV(7);
  
  VxD(8)  <= C(0);
  VxD(9)  <= C(1);
  VxD(10) <= C(2);
  VxD(11) <= C(3);
  VxD(12) <= TxD(0) xor C(4);
  VxD(13) <= TxD(0) xor C(5);
  VxD(14) <= TxD(1) xor C(6);
  VxD(15) <= TxD(1) xor C(7);

  -----------------------------------------------------------------------------
  -- ROUND
  -----------------------------------------------------------------------------
  u_roundreg: roundreg
    port map (
      CLKxCI   => CLKxCI,
      RSTxRBI  => RSTxRBI,
      WEIxSI   => InENxSI,
      ICNTxSI  => ICNTxS,
      ROUNDxSI => ROUNDxS,
      VxDI     => VxD,
      MxDI     => MxDP,
      VxDO     => VFxD
      );


  -----------------------------------------------------------------------------
  -- FINALIZATION
  -----------------------------------------------------------------------------
  HxDN(0) <= IV(0) when UseIVxS = '1' else (HxDP(0) xor VFxD(0) xor VFxD(8))  when NewChainxS = '1' else HxDP(0);
  HxDN(1) <= IV(1) when UseIVxS = '1' else (HxDP(1) xor VFxD(1) xor VFxD(9))  when NewChainxS = '1' else HxDP(1);
  HxDN(2) <= IV(2) when UseIVxS = '1' else (HxDP(2) xor VFxD(2) xor VFxD(10)) when NewChainxS = '1' else HxDP(2);
  HxDN(3) <= IV(3) when UseIVxS = '1' else (HxDP(3) xor VFxD(3) xor VFxD(11)) when NewChainxS = '1' else HxDP(3);
  HxDN(4) <= IV(4) when UseIVxS = '1' else (HxDP(4) xor VFxD(4) xor VFxD(12)) when NewChainxS = '1' else HxDP(4);
  HxDN(5) <= IV(5) when UseIVxS = '1' else (HxDP(5) xor VFxD(5) xor VFxD(13)) when NewChainxS = '1' else HxDP(5);
  HxDN(6) <= IV(6) when UseIVxS = '1' else (HxDP(6) xor VFxD(6) xor VFxD(14)) when NewChainxS = '1' else HxDP(6);
  HxDN(7) <= IV(7) when UseIVxS = '1' else (HxDP(7) xor VFxD(7) xor VFxD(15)) when NewChainxS = '1' else HxDP(7);

  -- M and H Memories
  -----------------------------------------------------------------------------
  p_mem: process (CLKxCI, RSTxRBI)
  begin  -- process p_mem
    if RSTxRBI = '0' then               -- asynchronous reset (active low)
      HxDP <= (others => (others => '0'));
      MxDP <= (others => (others => '0'));
      
    elsif CLKxCI'event and CLKxCI = '1' then  -- rising clock edge
      HxDP <= HxDN;
      MxDP <= MxDN;
      
    end if;
  end process p_mem;

end hash;