------------------------------------------------------------ -- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich -- http://www.iis.ee.ethz.ch/~sha3 ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.blakePkg.all; entity roundreg is port ( CLKxCI : in std_logic; RSTxRBI : in std_logic; WEIxSI : in std_logic; ROUNDxSI : in unsigned(4 downto 0); PROUNDxSI : in unsigned(4 downto 0); VxDI : in SUB16; MxDI : in SUB16; MIxDI : in SUB4; VxDO : out SUB16 ); end roundreg; architecture hash of roundreg is signal ROUNDxS, PROUNDxS : unsigned(3 downto 0); signal ICNTxS : unsigned(0 downto 0); signal EndswxS : std_logic; signal VxDN, VxDP : SUB16; signal G0MxD, G0KxD : std_logic_vector(WWIDTH*2-1 downto 0); signal G1MxD, G1KxD : std_logic_vector(WWIDTH*2-1 downto 0); signal G2MxD, G2KxD : std_logic_vector(WWIDTH*2-1 downto 0); signal G3MxD, G3KxD : std_logic_vector(WWIDTH*2-1 downto 0); signal G0AxD, G0BxD, G0CxD, G0DxD : std_logic_vector(WWIDTH-1 downto 0); signal G1AxD, G1BxD, G1CxD, G1DxD : std_logic_vector(WWIDTH-1 downto 0); signal G2AxD, G2BxD, G2CxD, G2DxD : std_logic_vector(WWIDTH-1 downto 0); signal G3AxD, G3BxD, G3CxD, G3DxD : std_logic_vector(WWIDTH-1 downto 0); signal G0AOxD, G0BOxD, G0COxD, G0DOxD : std_logic_vector(WWIDTH-1 downto 0); signal G1AOxD, G1BOxD, G1COxD, G1DOxD : std_logic_vector(WWIDTH-1 downto 0); signal G2AOxD, G2BOxD, G2COxD, G2DOxD : std_logic_vector(WWIDTH-1 downto 0); signal G3AOxD, G3BOxD, G3COxD, G3DOxD : std_logic_vector(WWIDTH-1 downto 0); signal T10xD, T20xD, T30xD, T40xD, T50xD, T60xD, Ti0xD : std_logic_vector(WWIDTH-1 downto 0); signal T70xD, T80xD, T90xD, TA0xD, TB0xD, TC0xD, To0xD : std_logic_vector(WWIDTH-1 downto 0); signal T11xD, T21xD, T31xD, T41xD, T51xD, T61xD, Ti1xD : std_logic_vector(WWIDTH-1 downto 0); signal T71xD, T81xD, T91xD, TA1xD, TB1xD, TC1xD, To1xD : std_logic_vector(WWIDTH-1 downto 0); signal T12xD, T22xD, T32xD, T42xD, T52xD, T62xD, Ti2xD : std_logic_vector(WWIDTH-1 downto 0); signal T72xD, T82xD, T92xD, TA2xD, TB2xD, TC2xD, To2xD : std_logic_vector(WWIDTH-1 downto 0); signal T13xD, T23xD, T33xD, T43xD, T53xD, T63xD, Ti3xD : std_logic_vector(WWIDTH-1 downto 0); signal T73xD, T83xD, T93xD, TA3xD, TB3xD, TC3xD, To3xD : std_logic_vector(WWIDTH-1 downto 0); signal C00xD, C10xD, C20xD, C30xD : std_logic_vector(WWIDTH-1 downto 0); signal C01xD, C11xD, C21xD, C31xD : std_logic_vector(WWIDTH-1 downto 0); signal M00xD, M10xD, M20xD, M30xD : std_logic_vector(WWIDTH-1 downto 0); signal M01xD, M11xD, M21xD, M31xD : std_logic_vector(WWIDTH-1 downto 0); signal MCxD : SUB4X2; begin -- hash VxDO <= VxDP; ROUNDxS <= ROUNDxSI(4 downto 1); PROUNDxS <= PROUNDxSI(4 downto 1); ----------------------------------------------------------------------------- -- MEMORY INPUTS ----------------------------------------------------------------------------- p_inmem: process (G0AOxD, G0BOxD, G0COxD, G0DOxD, G1AOxD, G1BOxD, G1COxD, G1DOxD, G2AOxD, G2BOxD, G2COxD, G2DOxD, G3AOxD, G3BOxD, G3COxD, G3DOxD, MIxDI, ROUNDxSI, VxDI, VxDP, WEIxSI) begin -- process p_inmem VxDN <= VxDP; if WEIxSI = '1' then -- VxDN(0) VxDI(0)) + unsigned(MCxD(0)(0))); -- VxDN(1) VxDI(1)) + unsigned(MCxD(1)(0))); -- VxDN(2) VxDI(2)) + unsigned(MCxD(2)(0))); -- VxDN(3) VxDI(3)) + unsigned(MCxD(3)(0))); VxDN(0) <= std_logic_vector(unsigned(VxDI(0)) + unsigned(MIxDI(0) xor C(1))); VxDN(1) <= std_logic_vector(unsigned(VxDI(1)) + unsigned(MIxDI(1) xor C(3))); VxDN(2) <= std_logic_vector(unsigned(VxDI(2)) + unsigned(MIxDI(2) xor C(5))); VxDN(3) <= std_logic_vector(unsigned(VxDI(3)) + unsigned(MIxDI(3) xor C(7))); VxDN(4) <= VxDI(4); VxDN(5) <= VxDI(5); VxDN(6) <= VxDI(6); VxDN(7) <= VxDI(7); VxDN(8) <= VxDI(8); VxDN(9) <= VxDI(9); VxDN(10) <= VxDI(10); VxDN(11) <= VxDI(11); VxDN(12) <= VxDI(12); VxDN(13) <= VxDI(13); VxDN(14) <= VxDI(14); VxDN(15) <= VxDI(15); elsif ROUNDxSI(0) = '0' then VxDN(0) <= G0AOxD; VxDN(7) <= G0BOxD; VxDN(10) <= G0COxD; VxDN(13) <= G0DOxD; VxDN(1) <= G1AOxD; VxDN(4) <= G1BOxD; VxDN(11) <= G1COxD; VxDN(14) <= G1DOxD; VxDN(2) <= G2AOxD; VxDN(5) <= G2BOxD; VxDN(8) <= G2COxD; VxDN(15) <= G2DOxD; VxDN(3) <= G3AOxD; VxDN(6) <= G3BOxD; VxDN(9) <= G3COxD; VxDN(12) <= G3DOxD; else VxDN(0) <= G0AOxD; VxDN(5) <= G0BOxD; VxDN(10) <= G0COxD; VxDN(15) <= G0DOxD; VxDN(1) <= G1AOxD; VxDN(6) <= G1BOxD; VxDN(11) <= G1COxD; VxDN(12) <= G1DOxD; VxDN(2) <= G2AOxD; VxDN(7) <= G2BOxD; VxDN(8) <= G2COxD; VxDN(13) <= G2DOxD; VxDN(3) <= G3AOxD; VxDN(4) <= G3BOxD; VxDN(9) <= G3COxD; VxDN(14) <= G3DOxD; end if; end process p_inmem; G0AxD <= VxDP(0); G0BxD <= VxDP(4); G0CxD <= VxDP(8); G0DxD <= VxDP(12); G1AxD <= VxDP(1); G1BxD <= VxDP(5); G1CxD <= VxDP(9); G1DxD <= VxDP(13); G2AxD <= VxDP(2); G2BxD <= VxDP(6); G2CxD <= VxDP(10); G2DxD <= VxDP(14); G3AxD <= VxDP(3); G3BxD <= VxDP(7); G3CxD <= VxDP(11); G3DxD <= VxDP(15); ----------------------------------------------------------------------------- -- MC PAIRS ----------------------------------------------------------------------------- p_mcsel0: process (MxDI, ROUNDxSI) begin -- process p_mcsel0 case ROUNDxSI is when "00000" => C01xD <= C( 0); M01xD <= MxDI( 1); C11xD <= C( 2); M11xD <= MxDI( 3); C21xD <= C( 4); M21xD <= MxDI( 5); C31xD <= C( 6); M31xD <= MxDI( 7); when "00010" => C01xD <= C(14); M01xD <= MxDI(10); C11xD <= C( 4); M11xD <= MxDI( 8); C21xD <= C( 9); M21xD <= MxDI(15); C31xD <= C(13); M31xD <= MxDI( 6); when "00100" => C01xD <= C(11); M01xD <= MxDI( 8); C11xD <= C(12); M11xD <= MxDI( 0); C21xD <= C( 5); M21xD <= MxDI( 2); C31xD <= C(15); M31xD <= MxDI(13); when "00110" => C01xD <= C( 7); M01xD <= MxDI( 9); C11xD <= C( 3); M11xD <= MxDI( 1); C21xD <= C(13); M21xD <= MxDI(12); C31xD <= C(11); M31xD <= MxDI(14); when "01000" => C01xD <= C( 9); M01xD <= MxDI( 0); C11xD <= C( 5); M11xD <= MxDI( 7); C21xD <= C( 2); M21xD <= MxDI( 4); C31xD <= C(10); M31xD <= MxDI(15); when "01010" => C01xD <= C( 2); M01xD <= MxDI(12); C11xD <= C( 6); M11xD <= MxDI(10); C21xD <= C( 0); M21xD <= MxDI(11); C31xD <= C( 8); M31xD <= MxDI( 3); when "01100" => C01xD <= C(12); M01xD <= MxDI( 5); C11xD <= C( 1); M11xD <= MxDI(15); C21xD <= C(14); M21xD <= MxDI(13); C31xD <= C( 4); M31xD <= MxDI(10); when "01110" => C01xD <= C(13); M01xD <= MxDI(11); C11xD <= C( 7); M11xD <= MxDI(14); C21xD <= C(12); M21xD <= MxDI( 1); C31xD <= C( 3); M31xD <= MxDI( 9); when "10000" => C01xD <= C( 6); M01xD <= MxDI(15); C11xD <= C(14); M11xD <= MxDI( 9); C21xD <= C(11); M21xD <= MxDI( 3); C31xD <= C( 0); M31xD <= MxDI( 8); when "10010" => C01xD <= C(10); M01xD <= MxDI( 2); C11xD <= C( 8); M11xD <= MxDI( 4); C21xD <= C( 7); M21xD <= MxDI( 6); C31xD <= C( 1); M31xD <= MxDI( 5); when "00001" => C01xD <= C( 8); M01xD <= MxDI( 9); C11xD <= C(10); M11xD <= MxDI(11); C21xD <= C(12); M21xD <= MxDI(13); C31xD <= C(14); M31xD <= MxDI(15); when "00011" => C01xD <= C( 1); M01xD <= MxDI(12); C11xD <= C( 0); M11xD <= MxDI( 2); C21xD <= C(11); M21xD <= MxDI( 7); C31xD <= C( 5); M31xD <= MxDI( 3); when "00101" => C01xD <= C(10); M01xD <= MxDI(14); C11xD <= C( 3); M11xD <= MxDI( 6); C21xD <= C( 7); M21xD <= MxDI( 1); C31xD <= C( 9); M31xD <= MxDI( 4); when "00111" => C01xD <= C( 2); M01xD <= MxDI( 6); C11xD <= C( 5); M11xD <= MxDI(10); C21xD <= C( 4); M21xD <= MxDI( 0); C31xD <= C(15); M31xD <= MxDI( 8); when "01001" => C01xD <= C(14); M01xD <= MxDI( 1); C11xD <= C(11); M11xD <= MxDI(12); C21xD <= C( 6); M21xD <= MxDI( 8); C31xD <= C( 3); M31xD <= MxDI(13); when "01011" => C01xD <= C( 4); M01xD <= MxDI(13); C11xD <= C( 7); M11xD <= MxDI( 5); C21xD <= C(15); M21xD <= MxDI(14); C31xD <= C( 1); M31xD <= MxDI( 9); when "01101" => C01xD <= C( 0); M01xD <= MxDI( 7); C11xD <= C( 6); M11xD <= MxDI( 3); C21xD <= C( 9); M21xD <= MxDI( 2); C31xD <= C( 8); M31xD <= MxDI(11); when "01111" => C01xD <= C( 5); M01xD <= MxDI( 0); C11xD <= C(15); M11xD <= MxDI( 4); C21xD <= C( 8); M21xD <= MxDI( 6); C31xD <= C( 2); M31xD <= MxDI(10); when "10001" => C01xD <= C(12); M01xD <= MxDI( 2); C11xD <= C(13); M11xD <= MxDI( 7); C21xD <= C( 1); M21xD <= MxDI( 4); C31xD <= C(10); M31xD <= MxDI( 5); when "10011" => C01xD <= C(15); M01xD <= MxDI(11); C11xD <= C( 9); M11xD <= MxDI(14); C21xD <= C( 3); M21xD <= MxDI(12); C31xD <= C(13); M31xD <= MxDI( 0); when others => C01xD <= (others => '0'); M01xD <= (others => '0'); C11xD <= (others => '0'); M11xD <= (others => '0'); C21xD <= (others => '0'); M21xD <= (others => '0'); C31xD <= (others => '0'); M31xD <= (others => '0'); end case; end process p_mcsel0; MCxD(0)(1) <= (M01xD xor C01xD); MCxD(1)(1) <= (M11xD xor C11xD); MCxD(2)(1) <= (M21xD xor C21xD); MCxD(3)(1) <= (M31xD xor C31xD); p_mcsel1: process (MxDI, PROUNDxSI) begin -- process p_mcsel1 case PROUNDxSI is when "00000" => C00xD <= C( 1); M00xD <= MxDI( 0); C10xD <= C( 3); M10xD <= MxDI( 2); C20xD <= C( 5); M20xD <= MxDI( 4); C30xD <= C( 7); M30xD <= MxDI( 6); when "00010" => C00xD <= C(10); M00xD <= MxDI(14); C10xD <= C( 8); M10xD <= MxDI( 4); C20xD <= C(15); M20xD <= MxDI( 9); C30xD <= C( 6); M30xD <= MxDI(13); when "00100" => C00xD <= C( 8); M00xD <= MxDI(11); C10xD <= C( 0); M10xD <= MxDI(12); C20xD <= C( 2); M20xD <= MxDI( 5); C30xD <= C(13); M30xD <= MxDI(15); when "00110" => C00xD <= C( 9); M00xD <= MxDI( 7); C10xD <= C( 1); M10xD <= MxDI( 3); C20xD <= C(12); M20xD <= MxDI(13); C30xD <= C(14); M30xD <= MxDI(11); when "01000" => C00xD <= C( 0); M00xD <= MxDI( 9); C10xD <= C( 7); M10xD <= MxDI( 5); C20xD <= C( 4); M20xD <= MxDI( 2); C30xD <= C(15); M30xD <= MxDI(10); when "01010" => C00xD <= C(12); M00xD <= MxDI( 2); C10xD <= C(10); M10xD <= MxDI( 6); C20xD <= C(11); M20xD <= MxDI( 0); C30xD <= C( 3); M30xD <= MxDI( 8); when "01100" => C00xD <= C( 5); M00xD <= MxDI(12); C10xD <= C(15); M10xD <= MxDI( 1); C20xD <= C(13); M20xD <= MxDI(14); C30xD <= C(10); M30xD <= MxDI( 4); when "01110" => C00xD <= C(11); M00xD <= MxDI(13); C10xD <= C(14); M10xD <= MxDI( 7); C20xD <= C( 1); M20xD <= MxDI(12); C30xD <= C( 9); M30xD <= MxDI( 3); when "10000" => C00xD <= C(15); M00xD <= MxDI( 6); C10xD <= C( 9); M10xD <= MxDI(14); C20xD <= C( 3); M20xD <= MxDI(11); C30xD <= C( 8); M30xD <= MxDI( 0); when "10010" => C00xD <= C( 2); M00xD <= MxDI(10); C10xD <= C( 4); M10xD <= MxDI( 8); C20xD <= C( 6); M20xD <= MxDI( 7); C30xD <= C( 5); M30xD <= MxDI( 1); when "00001" => C00xD <= C( 9); M00xD <= MxDI( 8); C10xD <= C(11); M10xD <= MxDI(10); C20xD <= C(13); M20xD <= MxDI(12); C30xD <= C(15); M30xD <= MxDI(14); when "00011" => C00xD <= C(12); M00xD <= MxDI( 1); C10xD <= C( 2); M10xD <= MxDI( 0); C20xD <= C( 7); M20xD <= MxDI(11); C30xD <= C( 3); M30xD <= MxDI( 5); when "00101" => C00xD <= C(14); M00xD <= MxDI(10); C10xD <= C( 6); M10xD <= MxDI( 3); C20xD <= C( 1); M20xD <= MxDI( 7); C30xD <= C( 4); M30xD <= MxDI( 9); when "00111" => C00xD <= C( 6); M00xD <= MxDI( 2); C10xD <= C(10); M10xD <= MxDI( 5); C20xD <= C( 0); M20xD <= MxDI( 4); C30xD <= C( 8); M30xD <= MxDI(15); when "01001" => C00xD <= C( 1); M00xD <= MxDI(14); C10xD <= C(12); M10xD <= MxDI(11); C20xD <= C( 8); M20xD <= MxDI( 6); C30xD <= C(13); M30xD <= MxDI( 3); when "01011" => C00xD <= C(13); M00xD <= MxDI( 4); C10xD <= C( 5); M10xD <= MxDI( 7); C20xD <= C(14); M20xD <= MxDI(15); C30xD <= C( 9); M30xD <= MxDI( 1); when "01101" => C00xD <= C( 7); M00xD <= MxDI( 0); C10xD <= C( 3); M10xD <= MxDI( 6); C20xD <= C( 2); M20xD <= MxDI( 9); C30xD <= C(11); M30xD <= MxDI( 8); when "01111" => C00xD <= C( 0); M00xD <= MxDI( 5); C10xD <= C( 4); M10xD <= MxDI(15); C20xD <= C( 6); M20xD <= MxDI( 8); C30xD <= C(10); M30xD <= MxDI( 2); when "10001" => C00xD <= C( 2); M00xD <= MxDI(12); C10xD <= C( 7); M10xD <= MxDI(13); C20xD <= C( 4); M20xD <= MxDI( 1); C30xD <= C( 5); M30xD <= MxDI(10); when "10011" => C00xD <= C(11); M00xD <= MxDI(15); C10xD <= C(14); M10xD <= MxDI( 9); C20xD <= C(12); M20xD <= MxDI( 3); C30xD <= C( 0); M30xD <= MxDI(13); when others => C00xD <= (others => '0'); M00xD <= (others => '0'); C10xD <= (others => '0'); M10xD <= (others => '0'); C20xD <= (others => '0'); M20xD <= (others => '0'); C30xD <= (others => '0'); M30xD <= (others => '0'); end case; end process p_mcsel1; MCxD(0)(0) <= (M00xD xor C00xD); MCxD(1)(0) <= (M10xD xor C10xD); MCxD(2)(0) <= (M20xD xor C20xD); MCxD(3)(0) <= (M30xD xor C30xD); ----------------------------------------------------------------------------- -- G BLOCKS ----------------------------------------------------------------------------- -- G0 / G4 ----------------------------------------------------------------------------- T10xD <= std_logic_vector(unsigned(G0AxD) + unsigned(G0BxD)); T20xD <= T10xD xor G0DxD; T30xD <= T20xD(15 downto 0) & T20xD(WWIDTH-1 downto 16); T40xD <= std_logic_vector(unsigned(G0CxD) + unsigned(T30xD)); T50xD <= T40xD xor G0BxD; T60xD <= T50xD(11 downto 0) & T50xD(WWIDTH-1 downto 12); Ti0xD <= std_logic_vector(unsigned(T10xD) + unsigned(MCxD(0)(1))); --------------------------------------------------------------------------- T70xD <= std_logic_vector(unsigned(Ti0xD) + unsigned(T60xD)); T80xD <= T70xD xor T30xD; T90xD <= T80xD(7 downto 0) & T80xD(WWIDTH-1 downto 8); TA0xD <= std_logic_vector(unsigned(T40xD) + unsigned(T90xD)); TB0xD <= TA0xD xor T60xD; TC0xD <= TB0xD(6 downto 0) & TB0xD(WWIDTH-1 downto 7); To0xD <= std_logic_vector(unsigned(T70xD) + unsigned(MCxD(0)(0))); G0AOxD <= To0xD; G0BOxD <= TC0xD; G0COxD <= TA0xD; G0DOxD <= T90xD; -- G1 / G5 ----------------------------------------------------------------------------- T11xD <= std_logic_vector(unsigned(G1AxD) + unsigned(G1BxD)); T21xD <= T11xD xor G1DxD; T31xD <= T21xD(15 downto 0) & T21xD(WWIDTH-1 downto 16); T41xD <= std_logic_vector(unsigned(G1CxD) + unsigned(T31xD)); T51xD <= T41xD xor G1BxD; T61xD <= T51xD(11 downto 0) & T51xD(WWIDTH-1 downto 12); Ti1xD <= std_logic_vector(unsigned(T11xD) + unsigned(MCxD(1)(1))); --------------------------------------------------------------------------- T71xD <= std_logic_vector(unsigned(Ti1xD) + unsigned(T61xD)); T81xD <= T71xD xor T31xD; T91xD <= T81xD(7 downto 0) & T81xD(WWIDTH-1 downto 8); TA1xD <= std_logic_vector(unsigned(T41xD) + unsigned(T91xD)); TB1xD <= TA1xD xor T61xD; TC1xD <= TB1xD(6 downto 0) & TB1xD(WWIDTH-1 downto 7); To1xD <= std_logic_vector(unsigned(T71xD) + unsigned(MCxD(1)(0))); G1AOxD <= To1xD; G1BOxD <= TC1xD; G1COxD <= TA1xD; G1DOxD <= T91xD; -- G2 / G6 ----------------------------------------------------------------------------- T12xD <= std_logic_vector(unsigned(G2AxD) + unsigned(G2BxD)); T22xD <= T12xD xor G2DxD; T32xD <= T22xD(15 downto 0) & T22xD(WWIDTH-1 downto 16); T42xD <= std_logic_vector(unsigned(G2CxD) + unsigned(T32xD)); T52xD <= T42xD xor G2BxD; T62xD <= T52xD(11 downto 0) & T52xD(WWIDTH-1 downto 12); Ti2xD <= std_logic_vector(unsigned(T12xD) + unsigned(MCxD(2)(1))); --------------------------------------------------------------------------- T72xD <= std_logic_vector(unsigned(Ti2xD) + unsigned(T62xD)); T82xD <= T72xD xor T32xD; T92xD <= T82xD(7 downto 0) & T82xD(WWIDTH-1 downto 8); TA2xD <= std_logic_vector(unsigned(T42xD) + unsigned(T92xD)); TB2xD <= TA2xD xor T62xD; TC2xD <= TB2xD(6 downto 0) & TB2xD(WWIDTH-1 downto 7); To2xD <= std_logic_vector(unsigned(T72xD) + unsigned(MCxD(2)(0))); G2AOxD <= To2xD; G2BOxD <= TC2xD; G2COxD <= TA2xD; G2DOxD <= T92xD; -- G3 / G7 ----------------------------------------------------------------------------- T13xD <= std_logic_vector(unsigned(G3AxD) + unsigned(G3BxD)); T23xD <= T13xD xor G3DxD; T33xD <= T23xD(15 downto 0) & T23xD(WWIDTH-1 downto 16); T43xD <= std_logic_vector(unsigned(G3CxD) + unsigned(T33xD)); T53xD <= T43xD xor G3BxD; T63xD <= T53xD(11 downto 0) & T53xD(WWIDTH-1 downto 12); Ti3xD <= std_logic_vector(unsigned(T13xD) + unsigned(MCxD(3)(1))); --------------------------------------------------------------------------- T73xD <= std_logic_vector(unsigned(Ti3xD) + unsigned(T63xD)); T83xD <= T73xD xor T33xD; T93xD <= T83xD(7 downto 0) & T83xD(WWIDTH-1 downto 8); TA3xD <= std_logic_vector(unsigned(T43xD) + unsigned(T93xD)); TB3xD <= TA3xD xor T63xD; TC3xD <= TB3xD(6 downto 0) & TB3xD(WWIDTH-1 downto 7); To3xD <= std_logic_vector(unsigned(T73xD) + unsigned(MCxD(3)(0))); G3AOxD <= To3xD; G3BOxD <= TC3xD; G3COxD <= TA3xD; G3DOxD <= T93xD; ----------------------------------------------------------------------------- -- v MEMORY ----------------------------------------------------------------------------- p_mem: process (CLKxCI, RSTxRBI) begin -- process p_vmem if RSTxRBI = '0' then -- asynchronous reset (active low) VxDP <= (others => (others => '0')); elsif CLKxCI'event and CLKxCI = '1' then -- rising clock edge VxDP <= VxDN; end if; end process p_mem; end hash;