------------------------------------------------------------
-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use work.blakePkg.all;

entity roundreg is
  port (
    CLKxCI   : in  std_logic;
    RSTxRBI  : in  std_logic;
    WEIxSI   : in  std_logic;
    ICNTxSI  : in  unsigned(3 downto 0);
    ROUNDxSI : in  unsigned(3 downto 0);
    VxDI     : in  SUB16;
    MxDI     : in  SUB16;
    VxDO     : out SUB16
    );

end roundreg;

architecture hash of roundreg is

  signal VxDN, VxDP, MxD                : SUB16;
  signal G0AxD, G0BxD, G0CxD, G0DxD     : std_logic_vector(WWIDTH-1 downto 0);
  signal G0MxD, G0KxD                   : std_logic_vector(WWIDTH-1 downto 0);
  signal G0AOxD, G0BOxD, G0COxD, G0DOxD : std_logic_vector(WWIDTH-1 downto 0);
  
  signal T1, T4         : unsigned(WWIDTH-1 downto 0);
  signal T2, T3, T5, T6 : std_logic_vector(WWIDTH-1 downto 0);
  
begin  -- hash

  VxDO <= VxDP;
  
  -----------------------------------------------------------------------------
  -- MEMORY INPUTS
  -----------------------------------------------------------------------------
  p_inmem: process (G0AOxD, G0BOxD, G0COxD, G0DOxD, VxDI, VxDP, WEIxSI, ICNTxSI)
  begin  -- process p_inmem

    VxDN <= VxDP;

    if WEIxSI = '1' then
      VxDN <= VxDI;

    else
      VxDN(IMATRIX(to_integer(ICNTxSI(3 downto 1)),  0)) <= G0AOxD;
      VxDN(IMATRIX(to_integer(ICNTxSI(3 downto 1)),  1)) <= G0BOxD;
      VxDN(IMATRIX(to_integer(ICNTxSI(3 downto 1)),  2)) <= G0COxD;
      VxDN(IMATRIX(to_integer(ICNTxSI(3 downto 1)),  3)) <= G0DOxD;
   
    end if;
  end process p_inmem;


  -----------------------------------------------------------------------------
  -- F AND G INPUTS
  -----------------------------------------------------------------------------
  p_outmem: process (ICNTxSI, MxDI, ROUNDxSI, VxDP)

    variable IND : integer;
    
  begin  -- process p_outmem

    IND := to_integer(ICNTxSI(3 downto 1));

    G0AxD <= VxDP(IMATRIX(IND, 0));
    G0BxD <= VxDP(IMATRIX(IND, 1));
    G0CxD <= VxDP(IMATRIX(IND, 2));
    G0DxD <= VxDP(IMATRIX(IND, 3));

    if ICNTxSI(0) = '0' then
      G0MxD <=  MxDI(PMATRIX(to_integer(ROUNDxSI), IND*2));
      G0KxD <=     C(PMATRIX(to_integer(ROUNDxSI), IND*2+1));

    else
      G0MxD <=  MxDI(PMATRIX(to_integer(ROUNDxSI), IND*2+1));
      G0KxD <=     C(PMATRIX(to_integer(ROUNDxSI), IND*2));
      
    end if;

  end process p_outmem;  


  -----------------------------------------------------------------------------
  -- PASS INSTANTIATION
  -----------------------------------------------------------------------------
  
  T1 <= unsigned(G0AxD) + unsigned(G0BxD) + unsigned(G0MxD xor G0KxD);
  T2 <= std_logic_vector(T1) xor G0DxD;
  T4 <= unsigned(G0CxD) + unsigned(T3);
  T5 <= std_logic_vector(T4) xor G0BxD;

  T3  <= T2(15 downto 0) & T2(WWIDTH-1 downto 16) when ICNTxSI(0) = '0' else T2(7 downto 0) & T2(WWIDTH-1 downto 8);
  T6  <= T5(11 downto 0) & T5(WWIDTH-1 downto 12) when ICNTxSI(0) = '0' else T5(6 downto 0) & T5(WWIDTH-1 downto 7);
  
  G0AOxD <= std_logic_vector(T1);
  G0BOxD <= T6;
  G0COxD <= std_logic_vector(T4);
  G0DOxD <= T3;

  
  -----------------------------------------------------------------------------
  -- V MEMORY
  -----------------------------------------------------------------------------
  
  p_mem: process (CLKxCI, RSTxRBI)
  begin  -- process p_vmem
    if RSTxRBI = '0' then               -- asynchronous reset (active low)
      VxDP <= (others => (others => '0'));
      
    elsif CLKxCI'event and CLKxCI = '1' then  -- rising clock edge
      VxDP <= VxDN;

    end if;
  end process p_mem;
  
end hash;