------------------------------------------------------------ -- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich -- http://www.iis.ee.ethz.ch/~sha3 ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use std.textio.all; use ieee.std_logic_textio.all; use work.blakePkg.all; entity roundreg is port ( CLKxCI : in std_logic; RSTxRBI : in std_logic; WEIxSI : in std_logic; ICNTxSI : in unsigned(2 downto 0); ROUNDxSI : in unsigned(3 downto 0); VxDI : in SUB16; MxDI : in SUB16; VxDO : out SUB16 ); end roundreg; architecture hash of roundreg is signal VxDN, VxDP, MxD : SUB16; signal G0AxD, G0BxD, G0CxD, G0DxD : std_logic_vector(WWIDTH-1 downto 0); signal G0MxD, G0KxD, G1MxD, G1KxD : std_logic_vector(WWIDTH-1 downto 0); signal G0AOxD, G0BOxD, G0COxD, G0DOxD : std_logic_vector(WWIDTH-1 downto 0); signal G0AZxD, G0BZxD, G0CZxD, G0DZxD : std_logic_vector(WWIDTH-1 downto 0); signal T1, T4 : unsigned(WWIDTH-1 downto 0); signal T2, T3, T5, T6 : std_logic_vector(WWIDTH-1 downto 0); signal T11, T44 : unsigned(WWIDTH-1 downto 0); signal T22, T33, T55, T66 : std_logic_vector(WWIDTH-1 downto 0); begin -- hash VxDO <= VxDP; ----------------------------------------------------------------------------- -- MEMORY INPUTS ----------------------------------------------------------------------------- p_inmem: process (G0AOxD, G0BOxD, G0COxD, G0DOxD, VxDI, VxDP, WEIxSI, ICNTxSI) begin -- process p_inmem VxDN <= VxDP; if WEIxSI = '1' then VxDN <= VxDI; else VxDN(IMATRIX(to_integer(ICNTxSI), 0)) <= G0AOxD; VxDN(IMATRIX(to_integer(ICNTxSI), 1)) <= G0BOxD; VxDN(IMATRIX(to_integer(ICNTxSI), 2)) <= G0COxD; VxDN(IMATRIX(to_integer(ICNTxSI), 3)) <= G0DOxD; end if; end process p_inmem; ----------------------------------------------------------------------------- -- F AND G INPUTS ----------------------------------------------------------------------------- p_outmem: process (ICNTxSI, MxDI, ROUNDxSI, VxDP) variable IND : integer; begin -- process p_outmem IND := to_integer(ICNTxSI); G0AxD <= VxDP(IMATRIX(IND, 0)); G0BxD <= VxDP(IMATRIX(IND, 1)); G0CxD <= VxDP(IMATRIX(IND, 2)); G0DxD <= VxDP(IMATRIX(IND, 3)); G0MxD <= MxDI(PMATRIX(to_integer(ROUNDxSI), IND*2)); G0KxD <= C(PMATRIX(to_integer(ROUNDxSI), IND*2+1)); G1MxD <= MxDI(PMATRIX(to_integer(ROUNDxSI), IND*2+1)); G1KxD <= C(PMATRIX(to_integer(ROUNDxSI), IND*2)); end process p_outmem; ----------------------------------------------------------------------------- -- PASS INSTANTIATION ----------------------------------------------------------------------------- T1 <= unsigned(G0AxD) + unsigned(G0BxD) + unsigned(G0MxD xor G0KxD); T2 <= std_logic_vector(T1) xor G0DxD; T3 <= T2(15 downto 0) & T2(WWIDTH-1 downto 16); T4 <= unsigned(G0CxD) + unsigned(T3); T5 <= std_logic_vector(T4) xor G0BxD; T6 <= T5(11 downto 0) & T5(WWIDTH-1 downto 12); G0AZxD <= std_logic_vector(T1); G0BZxD <= T6; G0CZxD <= std_logic_vector(T4); G0DZxD <= T3; T11 <= unsigned(G0AZxD) + unsigned(G0BZxD) + unsigned(G1MxD xor G1KxD); T22 <= std_logic_vector(T11) xor G0DZxD; T33 <= T22(7 downto 0) & T22(WWIDTH-1 downto 8); T44 <= unsigned(G0CZxD) + unsigned(T33); T55 <= std_logic_vector(T44) xor G0BZxD; T66 <= T55(6 downto 0) & T55(WWIDTH-1 downto 7); G0AOxD <= std_logic_vector(T11); G0BOxD <= T66; G0COxD <= std_logic_vector(T44); G0DOxD <= T33; ----------------------------------------------------------------------------- -- V MEMORY ----------------------------------------------------------------------------- p_mem: process (CLKxCI, RSTxRBI) begin -- process p_vmem if RSTxRBI = '0' then -- asynchronous reset (active low) VxDP <= (others => (others => '0')); elsif CLKxCI'event and CLKxCI = '1' then -- rising clock edge VxDP <= VxDN; end if; end process p_mem; end hash;