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-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
-- http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity bmw256 is
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
BlockAvailablexSI : in std_logic;
BlockxDI : in std_logic_vector(511 downto 0);
HashAvailablexSO : out std_logic;
HashxDO : out std_logic_vector(255 downto 0)
);
end bmw256;
architecture rtl of bmw256 is
component f0
port (
MxDI : in std_logic_vector(511 downto 0);
HxDI : in std_logic_vector(511 downto 0);
QaxDO : out std_logic_vector(511 downto 0));
end component;
component expand
port (
MxDI : in std_logic_vector(511 downto 0);
QbxDI : in std_logic_vector(511 downto 0);
QaxDI : in std_logic_vector(511 downto 0);
HxDI : in std_logic_vector(511 downto 0);
QbxDO : out std_logic_vector(31 downto 0);
ExpControlxSI : in std_logic_vector(4 downto 0));
end component;
component f2
port (
MxDI : in std_logic_vector(511 downto 0);
QbxDI : in std_logic_vector(511 downto 0);
QaxDI : in std_logic_vector(511 downto 0);
HxDO : out std_logic_vector(511 downto 0));
end component;
component controller
port (
BlockAvailablexSI : in std_logic;
ClkxCI : in std_logic;
RstxRBI : in std_logic;
MEnablexSO : out std_logic;
HEnablexSO : out std_logic;
HInitxSO : out std_logic;
FinalizexSO : out std_logic;
ExpControlxSO : out std_logic_vector(4 downto 0);
HashAvailablexSO : out std_logic);
end component;
signal MxD, QaxDN, QaxDP, QbxD, QbxDP, HxDP, HxDN, MmxD, HmxDN, HmxDP : std_logic_vector(511 downto 0);
signal QbxDN : std_logic_vector(31 downto 0);
signal MEnablexS, HEnablexS, HInitxS, FinalizexS, HashAvailablexS : std_logic;
signal ExpControlxS : std_logic_vector(4 downto 0);
signal WordSelectxS : integer;
constant CONSTFIN : std_logic_vector(511 downto 0) := (X"aaaaaaa0" & X"aaaaaaa1" & X"aaaaaaa2" & X"aaaaaaa3" &
X"aaaaaaa4" & X"aaaaaaa5" & X"aaaaaaa6" & X"aaaaaaa7" &
X"aaaaaaa8" & X"aaaaaaa9" & X"aaaaaaaa" & X"aaaaaaab" &
X"aaaaaaac" & X"aaaaaaad" & X"aaaaaaae" & X"aaaaaaaf");
constant H0 : std_logic_vector(511 downto 0) := (X"40414243" & X"44454647" & X"48494a4b" & X"4c4d4e4f" &
X"50515253" & X"54555657" & X"58595a5b" & X"5c5d5e5f" &
X"60616263" & X"64656667" & X"68696a6b" & X"6c6d6e6f" &
X"70717273" & X"74757677" & X"78797a7b" & X"7c7d7e7f");
begin -- rtl
i_controller : controller
port map (
BlockAvailablexSI => BlockAvailablexSI,
ClkxCI => ClkxCI,
RstxRBI => RstxRBI,
MEnablexSO => MEnablexS,
HEnablexSO => HEnablexS,
HInitxSO => HInitxS,
FinalizexSO => FinalizexS,
ExpControlxSO => ExpControlxS,
HashAvailablexSO => HashAvailablexS);
i_f0 : f0
port map (
MxDI => MxD,
HxDI => HxDP,
QaxDO => QaxDN);
i_expand : expand
port map (
MxDI => MxD,
QaxDI => QaxDP,
HxDI => HxDP,
QbxDI => QbxDP,
QbxDO => QbxDN,
ExpControlxSI => ExpControlxS);
i_f2 : f2
port map (
MxDI => MxD,
QbxDI => QbxDP,
QaxDI => QaxDP,
HxDO => HxDN);
-- M-register
-----------------------------------------------------------------------------
M_mem : process (ClkxCI, RstxRBI)
begin -- process M_mem
if RstxRBI = '0' then -- asynchronous reset (active low)
MmxD <= (others => '0');
elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge
if MEnablexS = '1' then
MmxD <= BlockxDI;
end if;
end if;
end process M_mem;
-- H-register
-----------------------------------------------------------------------------
H_mem : process (ClkxCI, RstxRBI)
begin -- process H_mem
if RstxRBI = '0' then -- asynchronous reset (active low)
HmxDP <= (others => '0');
elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge
if HEnablexS = '1' then
HmxDP <= HmxDN;
end if;
end if;
end process H_mem;
-- Qa-register
-----------------------------------------------------------------------------
Qa_mem : process (ClkxCI, RstxRBI)
begin -- process Qa_mem
if RstxRBI = '0' then -- asynchronous reset (active low)
QaxDP <= (others => '0');
elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge
QaxDP <= QaxDN;
end if;
end process Qa_mem;
-- Qb-register
-----------------------------------------------------------------------------
Qb_mem : process (ClkxCI, RstxRBI)
begin -- process Qb_mem
if RstxRBI = '0' then -- asynchronous reset (active low)
QbxDP <= (others => '0');
elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge
case WordSelectxS is
when 0 => QbxDP(511 downto 480) <= QbxDN;
when 1 => QbxDP(479 downto 448) <= QbxDN;
when 2 => QbxDP(447 downto 416) <= QbxDN;
when 3 => QbxDP(415 downto 384) <= QbxDN;
when 4 => QbxDP(383 downto 352) <= QbxDN;
when 5 => QbxDP(351 downto 320) <= QbxDN;
when 6 => QbxDP(319 downto 288) <= QbxDN;
when 7 => QbxDP(287 downto 256) <= QbxDN;
when 8 => QbxDP(255 downto 224) <= QbxDN;
when 9 => QbxDP(223 downto 192) <= QbxDN;
when 10 => QbxDP(191 downto 160) <= QbxDN;
when 11 => QbxDP(159 downto 128) <= QbxDN;
when 12 => QbxDP(127 downto 96) <= QbxDN;
when 13 => QbxDP(95 downto 64) <= QbxDN;
when 14 => QbxDP(63 downto 32) <= QbxDN;
when others => QbxDP(31 downto 0) <= QbxDN;
end case;
end if;
end process Qb_mem;
WordSelectxS <= to_integer(unsigned(ExpControlxS(3 downto 0)));
MxD <= MmxD when FinalizexS = '0' else HmxDP;
HxDP <= HmxDP when FinalizexS = '0' else CONSTFIN;
HmxDN <= HxDN when HInitxS = '0' else H0;
-- HashxDO HxDN(255 downto 0);
HashxDO <=
HxDN(231 downto 224) & HxDN(239 downto 232) & HxDN(247 downto 240) & HxDN(255 downto 248) &
HxDN(199 downto 192) & HxDN(207 downto 200) & HxDN(215 downto 208) & HxDN(223 downto 216) &
HxDN(167 downto 160) & HxDN(175 downto 168) & HxDN(183 downto 176) & HxDN(191 downto 184) &
HxDN(135 downto 128) & HxDN(143 downto 136) & HxDN(151 downto 144) & HxDN(159 downto 152) &
HxDN(103 downto 96) & HxDN(111 downto 104) & HxDN(119 downto 112) & HxDN(127 downto 120) &
HxDN(71 downto 64) & HxDN(79 downto 72) & HxDN(87 downto 80) & HxDN(95 downto 88) &
HxDN(39 downto 32) & HxDN(47 downto 40) & HxDN(55 downto 48) & HxDN(63 downto 56) &
HxDN(7 downto 0) & HxDN(15 downto 8) & HxDN(23 downto 16) & HxDN(31 downto 24);
HashAvailablexSO <= HashAvailablexS;
end rtl;