------------------------------------------------------------ -- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich -- http://www.iis.ee.ethz.ch/~sha3 ------------------------------------------------------------ library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; entity controller is port ( ClkxCI : in std_logic; RstxRBI : in std_logic; BlockAvailablexSI : in std_logic; HashAvailablexSO : out std_logic; MEnablexSO : out std_logic; HEnablexSO : out std_logic; HInitxSO : out std_logic; FinalizexSO : out std_logic; ExpControlxSO : out std_logic_vector(4 downto 0)); end controller; architecture rtl of controller is type state is (idle, f0, exp1_0, exp1_1, exp2_2, exp2_3, exp2_4, exp2_5, exp2_6, exp2_7, exp2_8, exp2_9, exp2_10, exp2_11, exp2_12, exp2_13, exp2_14, exp2_15, f2, F_f0, F_exp1_0, F_exp1_1, F_exp2_2, F_exp2_3, F_exp2_4, F_exp2_5, F_exp2_6, F_exp2_7, F_exp2_8, F_exp2_9, F_exp2_10, F_exp2_11, F_exp2_12, F_exp2_13, F_exp2_14, F_exp2_15, F_f2, waiting); signal StatexDP, StatexDN : state; begin -- rtl p_fsm : process (BlockAvailablexSI, StatexDP) begin -- process p_fsm StatexDN <= StatexDP; MEnablexSO <= '1'; HEnablexSO <= '1'; HInitxSO <= '1'; FinalizexSO <= '0'; ExpControlxSO <= (others => '0'); HashAvailablexSO <= '0'; case StatexDP is ------------------------------------------------------------------------- when idle => if BlockAvailablexSI = '1' then StatexDN <= f0; end if; MEnablexSO <= '1'; HEnablexSO <= '1'; HInitxSO <= '1'; FinalizexSO <= '0'; ExpControlxSO <= (others => '0'); HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when f0 => StatexDN <= exp1_0; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '0'; ExpControlxSO <= (others => '0'); HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when exp1_0 => StatexDN <= exp1_1; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '0'; ExpControlxSO <= "00000"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when exp1_1 => StatexDN <= exp2_2; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '0'; ExpControlxSO <= "00001"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when exp2_2 => StatexDN <= exp2_3; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '0'; ExpControlxSO <= "10010"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when exp2_3 => StatexDN <= exp2_4; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '0'; ExpControlxSO <= "10011"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when exp2_4 => StatexDN <= exp2_5; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '0'; ExpControlxSO <= "10100"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when exp2_5 => StatexDN <= exp2_6; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '0'; ExpControlxSO <= "10101"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when exp2_6 => StatexDN <= exp2_7; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '0'; ExpControlxSO <= "10110"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when exp2_7 => StatexDN <= exp2_8; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '0'; ExpControlxSO <= "10111"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when exp2_8 => StatexDN <= exp2_9; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '0'; ExpControlxSO <= "11000"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when exp2_9 => StatexDN <= exp2_10; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '0'; ExpControlxSO <= "11001"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when exp2_10 => StatexDN <= exp2_11; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '0'; ExpControlxSO <= "11010"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------ when exp2_11 => StatexDN <= exp2_12; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '0'; ExpControlxSO <= "11011"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when exp2_12 => StatexDN <= exp2_13; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '0'; ExpControlxSO <= "11100"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when exp2_13 => StatexDN <= exp2_14; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '0'; ExpControlxSO <= "11101"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when exp2_14 => StatexDN <= exp2_15; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '0'; ExpControlxSO <= "11110"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when exp2_15 => StatexDN <= f2; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '0'; ExpControlxSO <= "11111"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when f2 => if BlockAvailablexSI = '1' then StatexDN <= f0; else StatexDN <= F_f0; end if; MEnablexSO <= '1'; HEnablexSO <= '1'; HInitxSO <= '0'; FinalizexSO <= '0'; ExpControlxSO <= (others => '0'); HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when F_f0 => StatexDN <= F_exp1_0; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '1'; ExpControlxSO <= (others => '0'); HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when F_exp1_0 => StatexDN <= F_exp1_1; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '1'; ExpControlxSO <= "00000"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when F_exp1_1 => StatexDN <= F_exp2_2; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '1'; ExpControlxSO <= "00001"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when F_exp2_2 => StatexDN <= F_exp2_3; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '1'; ExpControlxSO <= "10010"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when F_exp2_3 => StatexDN <= F_exp2_4; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '1'; ExpControlxSO <= "10011"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when F_exp2_4 => StatexDN <= F_exp2_5; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '1'; ExpControlxSO <= "10100"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when F_exp2_5 => StatexDN <= F_exp2_6; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '1'; ExpControlxSO <= "10101"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when F_exp2_6 => StatexDN <= F_exp2_7; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '1'; ExpControlxSO <= "10110"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when F_exp2_7 => StatexDN <= F_exp2_8; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '1'; ExpControlxSO <= "10111"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when F_exp2_8 => StatexDN <= F_exp2_9; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '1'; ExpControlxSO <= "11000"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when F_exp2_9 => StatexDN <= F_exp2_10; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '1'; ExpControlxSO <= "11001"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when F_exp2_10 => StatexDN <= F_exp2_11; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '1'; ExpControlxSO <= "11010"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------ when F_exp2_11 => StatexDN <= F_exp2_12; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '1'; ExpControlxSO <= "11011"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when F_exp2_12 => StatexDN <= F_exp2_13; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '1'; ExpControlxSO <= "11100"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when F_exp2_13 => StatexDN <= F_exp2_14; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '1'; ExpControlxSO <= "11101"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when F_exp2_14 => StatexDN <= F_exp2_15; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '1'; ExpControlxSO <= "11110"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when F_exp2_15 => StatexDN <= F_f2; MEnablexSO <= '0'; HEnablexSO <= '0'; HInitxSO <= '0'; FinalizexSO <= '1'; ExpControlxSO <= "11111"; HashAvailablexSO <= '0'; ------------------------------------------------------------------------- when F_f2 => if BlockAvailablexSI = '1' then StatexDN <= f0; else StatexDN <= idle; end if; MEnablexSO <= '1'; HEnablexSO <= '1'; HInitxSO <= '1'; FinalizexSO <= '1'; ExpControlxSO <= (others => '0'); HashAvailablexSO <= '1'; ------------------------------------------------------------------------- when others => StatexDN <= idle; end case; end process p_fsm; p_mem : process (ClkxCI, RstxRBI) begin -- process p_mem if RstxRBI = '0' then -- asynchronous reset (active low) StatexDP <= idle; elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge StatexDP <= StatexDN; end if; end process p_mem; end rtl;