------------------------------------------------------------ -- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich -- http://www.iis.ee.ethz.ch/~sha3 ------------------------------------------------------------ library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; entity expand is port ( MxDI : in std_logic_vector(511 downto 0); HxDI : in std_logic_vector(511 downto 0); QaxDI : in std_logic_vector(511 downto 0); QbxDI : in std_logic_vector(511 downto 0); QbxDO : out std_logic_vector(31 downto 0); ExpControlxSI : in std_logic_vector(4 downto 0)); end expand; architecture rtl of expand is signal JaxS, JbxS, JcxS, JdxS : integer; signal QbxD : std_logic_vector(31 downto 0); signal QxD : std_logic_vector(1023 downto 0); signal KxD : std_logic_vector(31 downto 0); signal CntxD : unsigned(3 downto 0); type qarray is array (0 to 31) of unsigned(31 downto 0); signal QqxD : qarray; type marray is array (0 to 15) of unsigned(31 downto 0); signal MmxD : marray; type harray is array (0 to 15) of unsigned(31 downto 0); signal HhxD : harray; begin -- rtl CntxD <= unsigned(ExpControlxSI(3 downto 0)); QxD <= QaxDI & QbxDI; qq_gen : for i in 0 to 15 generate QqxD(i) <= unsigned(QaxDI((16-i)*32-1 downto (16-i-1)*32)); QqxD(16+i) <= unsigned(QbxDI((16-i)*32-1 downto (16-i-1)*32)); end generate qq_gen; mm_gen : for i in 0 to 15 generate MmxD(i) <= unsigned(MxDI((16-i)*32-1 downto (16-i-1)*32)); end generate mm_gen; hh_gen : for i in 0 to 15 generate HhxD(i) <= unsigned(HxDI((16-i)*32-1 downto (16-i-1)*32)); end generate hh_gen; JaxS <= to_integer(unsigned(ExpControlxSI(3 downto 0))); -- this is mod(j,16) JbxS <= to_integer(unsigned(ExpControlxSI(3 downto 0)) + 3); -- this is mod(j+3,16) JcxS <= to_integer(unsigned(ExpControlxSI(3 downto 0)) + 10); -- this is mod(j+10,16) JdxS <= to_integer(unsigned(ExpControlxSI(3 downto 0)) + 7); -- this is mod(j+7,16) with JaxS select KxD <= x"55555550" when 0, x"5AAAAAA5" when 1, x"5FFFFFFA" when 2, x"6555554F" when 3, x"6AAAAAA4" when 4, x"6FFFFFF9" when 5, x"7555554E" when 6, x"7AAAAAA3" when 7, x"7FFFFFF8" when 8, x"8555554D" when 9, x"8AAAAAA2" when 10, x"8FFFFFF7" when 11, x"9555554C" when 12, x"9AAAAAA1" when 13, x"9FFFFFF6" when 14, x"A555554B" when others; combiexpand : process (CntxD, ExpControlxSI, HhxD, JaxS, JbxS, JcxS, JdxS, KxD, MmxD, QqxD) variable JxS : integer := 0; begin -- process combiexpand JxS := to_integer(CntxD); QbxD <= (others => '0'); if ExpControlxSI(4) = '0' then QbxD <= std_logic_vector(((QqxD(JxS) srl 1) xor (QqxD(JxS) sll 2) xor (QqxD(JxS) rol 8) xor (QqxD(JxS) rol 23)) + ((QqxD(JxS+1) srl 2) xor (QqxD(JxS+1) sll 1) xor (QqxD(JxS+1) rol 12) xor (QqxD(JxS+1) rol 25)) + ((QqxD(JxS+2) srl 2) xor (QqxD(JxS+2) sll 2) xor (QqxD(JxS+2) rol 15) xor (QqxD(JxS+2) rol 29)) + ((QqxD(JxS+3) srl 1) xor (QqxD(JxS+3) sll 3) xor (QqxD(JxS+3) rol 4) xor (QqxD(JxS+3) rol 19)) + ((QqxD(JxS+4) srl 1) xor (QqxD(JxS+4) sll 2) xor (QqxD(JxS+4) rol 8) xor (QqxD(JxS+4) rol 23)) + ((QqxD(JxS+5) srl 2) xor (QqxD(JxS+5) sll 1) xor (QqxD(JxS+5) rol 12) xor (QqxD(JxS+5) rol 25)) + ((QqxD(JxS+6) srl 2) xor (QqxD(JxS+6) sll 2) xor (QqxD(JxS+6) rol 15) xor (QqxD(JxS+6) rol 29)) + ((QqxD(JxS+7) srl 1) xor (QqxD(JxS+7) sll 3) xor (QqxD(JxS+7) rol 4) xor (QqxD(JxS+7) rol 19)) + ((QqxD(JxS+8) srl 1) xor (QqxD(JxS+8) sll 2) xor (QqxD(JxS+8) rol 8) xor (QqxD(JxS+8) rol 23)) + ((QqxD(JxS+9) srl 2) xor (QqxD(JxS+9) sll 1) xor (QqxD(JxS+9) rol 12) xor (QqxD(JxS+9) rol 25)) + ((QqxD(JxS+10) srl 2) xor (QqxD(JxS+10) sll 2) xor (QqxD(JxS+10) rol 15) xor (QqxD(JxS+10) rol 29)) + ((QqxD(JxS+11) srl 1) xor (QqxD(JxS+11) sll 3) xor (QqxD(JxS+11) rol 4) xor (QqxD(JxS+11) rol 19)) + ((QqxD(JxS+12) srl 1) xor (QqxD(JxS+12) sll 2) xor (QqxD(JxS+12) rol 8) xor (QqxD(JxS+12) rol 23)) + ((QqxD(JxS+13) srl 2) xor (QqxD(JxS+13) sll 1) xor (QqxD(JxS+13) rol 12) xor (QqxD(JxS+13) rol 25)) + ((QqxD(JxS+14) srl 2) xor (QqxD(JxS+14) sll 2) xor (QqxD(JxS+14) rol 15) xor (QqxD(JxS+14) rol 29)) + ((QqxD(JxS+15) srl 1) xor (QqxD(JxS+15) sll 3) xor (QqxD(JxS+15) rol 4) xor (QqxD(JxS+15) rol 19)) + (((MmxD(JaxS) rol (JaxS+1)) + (MmxD(JbxS) rol (JbxS+1)) - (MmxD(JcxS) rol (JcxS+1)) + unsigned(KxD)) xor HhxD(JdxS))); elsif ExpControlxSI(4) = '1' then QbxD <= std_logic_vector(QqxD(JxS) + (QqxD(JxS+1) rol 3) + QqxD(JxS+2) + (QqxD(JxS+3) rol 7) + QqxD(JxS+4) + (QqxD(JxS+5) rol 13) + QqxD(JxS+6) + (QqxD(JxS+7) rol 16) + QqxD(JxS+8) + (QqxD(JxS+9) rol 19) + QqxD(JxS+10) + (QqxD(JxS+11) rol 23) + QqxD(JxS+12) + (QqxD(JxS+13) rol 27) + ((QqxD(JxS+14) srl 1) xor QqxD(JxS+14)) + ((QqxD(JxS+15) srl 2) xor QqxD(JxS+15)) + (((MmxD(JaxS) rol (JaxS+1)) + (MmxD(JbxS) rol (JbxS+1)) - (MmxD(JcxS) rol (JcxS+1)) + unsigned(KxD)) xor HhxD(JdxS))); end if; end process combiexpand; QbxDO <= QbxD; end rtl;