bmw/sourcecode/f0.vhd

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-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
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library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity f0 is

  port (
    MxDI     : in  std_logic_vector(511 downto 0);
    HxDI     : in  std_logic_vector(511 downto 0);
    QaxDO    : out std_logic_vector(511 downto 0));

end f0;

architecture rtl of f0 is

  signal WxD : std_logic_vector(511 downto 0);
 
begin  -- rtl

WxD(511 downto 480) <=  std_logic_vector(unsigned(MxDI(351 downto 320) xor HxDI(351 downto 320)) - unsigned(MxDI(287 downto 256) xor HxDI(287 downto 256)) + unsigned(MxDI(191 downto 160) xor HxDI(191 downto 160)) + unsigned(MxDI(95 downto 64) xor HxDI(95 downto 64)) + unsigned(MxDI(63 downto 32) xor HxDI(63 downto 32)));
WxD(479 downto 448) <=  std_logic_vector(unsigned(MxDI(319 downto 288) xor HxDI(319 downto 288)) - unsigned(MxDI(255 downto 224) xor HxDI(255 downto 224)) + unsigned(MxDI(159 downto 128) xor HxDI(159 downto 128)) + unsigned(MxDI(63 downto 32) xor HxDI(63 downto 32)) - unsigned(MxDI(31 downto 0) xor HxDI(31 downto 0)));
WxD(447 downto 416) <=  std_logic_vector(unsigned(MxDI(511 downto 480) xor HxDI(511 downto 480)) + unsigned(MxDI(287 downto 256) xor HxDI(287 downto 256)) + unsigned(MxDI(223 downto 192) xor HxDI(223 downto 192)) - unsigned(MxDI(127 downto 96) xor HxDI(127 downto 96)) + unsigned(MxDI(31 downto 0) xor HxDI(31 downto 0)));
WxD(415 downto 384) <=  std_logic_vector(unsigned(MxDI(511 downto 480) xor HxDI(511 downto 480)) - unsigned(MxDI(479 downto 448) xor HxDI(479 downto 448)) + unsigned(MxDI(255 downto 224) xor HxDI(255 downto 224)) - unsigned(MxDI(191 downto 160) xor HxDI(191 downto 160)) + unsigned(MxDI(95 downto 64) xor HxDI(95 downto 64)));
WxD(383 downto 352) <=  std_logic_vector(unsigned(MxDI(479 downto 448) xor HxDI(479 downto 448)) + unsigned(MxDI(447 downto 416) xor HxDI(447 downto 416)) + unsigned(MxDI(223 downto 192) xor HxDI(223 downto 192)) - unsigned(MxDI(159 downto 128) xor HxDI(159 downto 128)) - unsigned(MxDI(63 downto 32) xor HxDI(63 downto 32)));
WxD(351 downto 320) <=  std_logic_vector(unsigned(MxDI(415 downto 384) xor HxDI(415 downto 384)) - unsigned(MxDI(447 downto 416) xor HxDI(447 downto 416)) + unsigned(MxDI(191 downto 160) xor HxDI(191 downto 160)) - unsigned(MxDI(127 downto 96) xor HxDI(127 downto 96)) + unsigned(MxDI(31 downto 0) xor HxDI(31 downto 0)));
WxD(319 downto 288) <=  std_logic_vector(unsigned(MxDI(383 downto 352) xor HxDI(383 downto 352)) - unsigned(MxDI(511 downto 480) xor HxDI(511 downto 480)) - unsigned(MxDI(415 downto 384) xor HxDI(415 downto 384)) - unsigned(MxDI(159 downto 128) xor HxDI(159 downto 128)) + unsigned(MxDI(95 downto 64) xor HxDI(95 downto 64)));
WxD(287 downto 256) <=  std_logic_vector(unsigned(MxDI(479 downto 448) xor HxDI(479 downto 448)) - unsigned(MxDI(383 downto 352) xor HxDI(383 downto 352)) - unsigned(MxDI(351 downto 320) xor HxDI(351 downto 320)) - unsigned(MxDI(127 downto 96) xor HxDI(127 downto 96)) - unsigned(MxDI(63 downto 32) xor HxDI(63 downto 32)));
WxD(255 downto 224) <=  std_logic_vector(unsigned(MxDI(447 downto 416) xor HxDI(447 downto 416)) - unsigned(MxDI(351 downto 320) xor HxDI(351 downto 320)) - unsigned(MxDI(319 downto 288) xor HxDI(319 downto 288)) + unsigned(MxDI(95 downto 64) xor HxDI(95 downto 64)) - unsigned(MxDI(31 downto 0) xor HxDI(31 downto 0)));
WxD(223 downto 192) <=  std_logic_vector(unsigned(MxDI(511 downto 480) xor HxDI(511 downto 480)) - unsigned(MxDI(415 downto 384) xor HxDI(415 downto 384)) + unsigned(MxDI(319 downto 288) xor HxDI(319 downto 288)) - unsigned(MxDI(287 downto 256) xor HxDI(287 downto 256)) + unsigned(MxDI(63 downto 32) xor HxDI(63 downto 32)));
WxD(191 downto 160) <=  std_logic_vector(unsigned(MxDI(255 downto 224) xor HxDI(255 downto 224)) - unsigned(MxDI(479 downto 448) xor HxDI(479 downto 448)) - unsigned(MxDI(383 downto 352) xor HxDI(383 downto 352)) - unsigned(MxDI(287 downto 256) xor HxDI(287 downto 256)) + unsigned(MxDI(31 downto 0) xor HxDI(31 downto 0)));
WxD(159 downto 128) <=  std_logic_vector(unsigned(MxDI(255 downto 224) xor HxDI(255 downto 224)) - unsigned(MxDI(511 downto 480) xor HxDI(511 downto 480)) - unsigned(MxDI(447 downto 416) xor HxDI(447 downto 416)) - unsigned(MxDI(351 downto 320) xor HxDI(351 downto 320)) + unsigned(MxDI(223 downto 192) xor HxDI(223 downto 192)));
WxD(127 downto 96)  <=  std_logic_vector(unsigned(MxDI(479 downto 448) xor HxDI(479 downto 448)) + unsigned(MxDI(415 downto 384) xor HxDI(415 downto 384)) - unsigned(MxDI(319 downto 288) xor HxDI(319 downto 288)) - unsigned(MxDI(223 downto 192) xor HxDI(223 downto 192)) + unsigned(MxDI(191 downto 160) xor HxDI(191 downto 160)));
WxD(95 downto 64)   <=  std_logic_vector(unsigned(MxDI(447 downto 416) xor HxDI(447 downto 416)) + unsigned(MxDI(383 downto 352) xor HxDI(383 downto 352)) + unsigned(MxDI(287 downto 256) xor HxDI(287 downto 256)) + unsigned(MxDI(191 downto 160) xor HxDI(191 downto 160)) + unsigned(MxDI(159 downto 128) xor HxDI(159 downto 128)));
WxD(63 downto 32)   <=  std_logic_vector(unsigned(MxDI(415 downto 384) xor HxDI(415 downto 384)) - unsigned(MxDI(351 downto 320) xor HxDI(351 downto 320)) + unsigned(MxDI(255 downto 224) xor HxDI(255 downto 224)) - unsigned(MxDI(159 downto 128) xor HxDI(159 downto 128)) - unsigned(MxDI(127 downto 96) xor HxDI(127 downto 96)));
WxD(31 downto 0)    <=  std_logic_vector(unsigned(MxDI(127 downto 96) xor HxDI(127 downto 96)) - unsigned(MxDI(383 downto 352) xor HxDI(383 downto 352)) - unsigned(MxDI(319 downto 288) xor HxDI(319 downto 288)) - unsigned(MxDI(223 downto 192) xor HxDI(223 downto 192)) + unsigned(MxDI(95 downto 64) xor HxDI(95 downto 64)));


QaxDO(511 downto 480) <= std_logic_vector(unsigned(std_logic_vector(unsigned(WxD(511 downto 480)) srl 1) xor std_logic_vector(unsigned(WxD(511 downto 480)) sll 3) xor std_logic_vector(unsigned(WxD(511 downto 480)) rol 4) xor std_logic_vector(unsigned(WxD(511 downto 480)) rol 19)) + unsigned(HxDI(479 downto 448)));
QaxDO(479 downto 448) <= std_logic_vector(unsigned(std_logic_vector(unsigned(WxD(479 downto 448)) srl 1) xor std_logic_vector(unsigned(WxD(479 downto 448)) sll 2) xor std_logic_vector(unsigned(WxD(479 downto 448)) rol 8) xor std_logic_vector(unsigned(WxD(479 downto 448)) rol 23)) + unsigned(HxDI(447 downto 416)));
QaxDO(447 downto 416) <= std_logic_vector(unsigned(std_logic_vector(unsigned(WxD(447 downto 416)) srl 2) xor std_logic_vector(unsigned(WxD(447 downto 416)) sll 1) xor std_logic_vector(unsigned(WxD(447 downto 416)) rol 12) xor std_logic_vector(unsigned(WxD(447 downto 416)) rol 25)) + unsigned(HxDI(415 downto 384)));
QaxDO(415 downto 384) <= std_logic_vector(unsigned(std_logic_vector(unsigned(WxD(415 downto 384)) srl 2) xor std_logic_vector(unsigned(WxD(415 downto 384)) sll 2) xor std_logic_vector(unsigned(WxD(415 downto 384)) rol 15) xor std_logic_vector(unsigned(WxD(415 downto 384)) rol 29)) + unsigned(HxDI(383 downto 352)));

QaxDO(383 downto 352) <= std_logic_vector(unsigned(std_logic_vector(unsigned(WxD(383 downto 352)) srl 1) xor std_logic_vector(unsigned(WxD(383 downto 352)))) + unsigned(HxDI(351 downto 320)));
                                          
QaxDO(351 downto 320) <= std_logic_vector(unsigned(std_logic_vector(unsigned(WxD(351 downto 320)) srl 1) xor std_logic_vector(unsigned(WxD(351 downto 320)) sll 3) xor std_logic_vector(unsigned(WxD(351 downto 320)) rol 4) xor std_logic_vector(unsigned(WxD(351 downto 320)) rol 19)) + unsigned(HxDI(319 downto 288)));
QaxDO(319 downto 288) <= std_logic_vector(unsigned(std_logic_vector(unsigned(WxD(319 downto 288)) srl 1) xor std_logic_vector(unsigned(WxD(319 downto 288)) sll 2) xor std_logic_vector(unsigned(WxD(319 downto 288)) rol 8) xor std_logic_vector(unsigned(WxD(319 downto 288)) rol 23)) + unsigned(HxDI(287 downto 256)));
QaxDO(287 downto 256) <= std_logic_vector(unsigned(std_logic_vector(unsigned(WxD(287 downto 256)) srl 2) xor std_logic_vector(unsigned(WxD(287 downto 256)) sll 1) xor std_logic_vector(unsigned(WxD(287 downto 256)) rol 12) xor std_logic_vector(unsigned(WxD(287 downto 256)) rol 25)) + unsigned(HxDI(255 downto 224)));
QaxDO(255 downto 224) <= std_logic_vector(unsigned(std_logic_vector(unsigned(WxD(255 downto 224)) srl 2) xor std_logic_vector(unsigned(WxD(255 downto 224)) sll 2) xor std_logic_vector(unsigned(WxD(255 downto 224)) rol 15) xor std_logic_vector(unsigned(WxD(255 downto 224)) rol 29)) + unsigned(HxDI(223 downto 192)));

QaxDO(223 downto 192) <= std_logic_vector(unsigned(std_logic_vector(unsigned(WxD(223 downto 192)) srl 1) xor std_logic_vector(unsigned(WxD(223 downto 192)))) + unsigned(HxDI(191 downto 160)));
                                          
QaxDO(191 downto 160) <= std_logic_vector(unsigned(std_logic_vector(unsigned(WxD(191 downto 160)) srl 1) xor std_logic_vector(unsigned(WxD(191 downto 160)) sll 3) xor std_logic_vector(unsigned(WxD(191 downto 160)) rol 4) xor std_logic_vector(unsigned(WxD(191 downto 160)) rol 19)) + unsigned(HxDI(159 downto 128)));
QaxDO(159 downto 128) <= std_logic_vector(unsigned(std_logic_vector(unsigned(WxD(159 downto 128)) srl 1) xor std_logic_vector(unsigned(WxD(159 downto 128)) sll 2) xor std_logic_vector(unsigned(WxD(159 downto 128)) rol 8) xor std_logic_vector(unsigned(WxD(159 downto 128)) rol 23)) + unsigned(HxDI(127 downto 96)));
QaxDO(127 downto 96)  <= std_logic_vector(unsigned(std_logic_vector(unsigned(WxD(127 downto 96))  srl 2) xor std_logic_vector(unsigned(WxD(127 downto 96))  sll 1) xor std_logic_vector(unsigned(WxD(127 downto 96)) rol 12) xor std_logic_vector(unsigned(WxD(127 downto 96)) rol 25)) + unsigned(HxDI(95 downto 64)));
QaxDO(95 downto 64)   <= std_logic_vector(unsigned(std_logic_vector(unsigned(WxD(95  downto 64))  srl 2) xor std_logic_vector(unsigned(WxD(95  downto 64))  sll 2) xor std_logic_vector(unsigned(WxD(95  downto 64)) rol 15) xor std_logic_vector(unsigned(WxD(95 downto 64)) rol 29)) + unsigned(HxDI(63 downto 32)));

QaxDO(63 downto 32)   <= std_logic_vector(unsigned(std_logic_vector(unsigned(WxD(63  downto 32))  srl 1) xor std_logic_vector(unsigned(WxD(63  downto 32)))) + unsigned(HxDI(31 downto 0)));

QaxDO(31 downto 0)    <= std_logic_vector(unsigned(std_logic_vector(unsigned(WxD(31  downto 0))   srl 1) xor std_logic_vector(unsigned(WxD(31  downto 0))   sll 3) xor std_logic_vector(unsigned(WxD(31  downto 0)) rol 4) xor std_logic_vector(unsigned(WxD(31 downto 0)) rol 19)) + unsigned(HxDI(511 downto 480)));

end rtl;
Generated on Fri Sep 24 10:39:12 CEST 2010
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