#! /bin/tcsh -f

############################################################
## Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich
##            http://www.iis.ee.ethz.ch/~sha3
############################################################
# v0.2 -  - Tue Aug 23 10:54:15 CEST 2011
#  - changed the way the last echo is displayed for a command line
#  - added an alg variable 
# v0.1 -  - Tue Aug 23 10:44:34 CEST 2011
# adapted to the new script
# Example script for compiling RTL sourcecode

set VER=10.0b
set LIB=rtl
set ALG=blake
set LOG=${ALG}_compile.log

if (-e $LIB) then
  echo "- Deleting old library [$LIB]"
  rm -rf $LIB 
endif

vlib-${VER} $LIB
echo -n "** Compilation of ${ALG} from: " >${LOG}
date >> ${LOG}

# compile sourcecode
vcom-${VER}  -work $LIB -check_synthesis ../sourcecode/blake256Pkg.vhd       >> ${LOG}
vcom-${VER}  -work $LIB -check_synthesis ../sourcecode/gcomp256.vhd          >> ${LOG}
vcom-${VER}  -work $LIB -check_synthesis ../sourcecode/roundreg.vhd          >> ${LOG}
vcom-${VER}  -work $LIB -check_synthesis ../sourcecode/controller.vhd        >> ${LOG}
vcom-${VER}  -work $LIB -check_synthesis ../sourcecode/initialization.vhd    >> ${LOG}
vcom-${VER}  -work $LIB -check_synthesis ../sourcecode/finalization.vhd      >> ${LOG}
vcom-${VER}  -work $LIB -check_synthesis ../sourcecode/blake.vhd             >> ${LOG}
vcom-${VER}  -work $LIB -check_synthesis ../sourcecode/blake_wrapper.vhd     >> ${LOG}

# testbench (note no -check_synthesis)
vcom-${VER}  -work $LIB ../sourcecode/simulstuff.vhd                         >> ${LOG}
vcom-${VER}  -work $LIB ../sourcecode/${ALG}_tb.vhd                          >> ${LOG}


#vmake-${VER}  rtl > Makefile
echo "- Reporting Warnings:"
grep -i "** Warn" ${LOG} | nl
echo "- Reporting Errors:"
grep -i "** Err" ${LOG} | grep -v "Compiler exiting" | nl
echo "* Done"


echo ""
echo "   vsim-${VER} -c  -lib ${LIB}  ${ALG}_tb -do "\""run -all; quit"\"" | tee ../simvectors/${ALG}_sim.rpt"
echo ""