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-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity controller is

  port (
    ClkxCI    : in  std_logic;
    RstxRBI   : in  std_logic;
    StartxSI  : in  std_logic;
    INENxEI   : in  std_logic;
    OUTENxEO  : out std_logic;
    XOR1xSO   : out std_logic;
    SwitchxSO : out std_logic);

end controller;

architecture rtl of controller is

  type state is (idle, round, fin);
  signal StatexDP, StatexDN : state;

  signal RcntxDP, RcntxDN     : unsigned(4 downto 0);
  signal TENcntxDP, TENcntxDN : unsigned(3 downto 0);
  
begin  -- rtl

  SwitchxSO <= RcntxDP(0);

  p_fsm: process (INENxEI, RcntxDP, StartxSI, StatexDP, TENcntxDP)
  begin  -- process p_fsm

    StatexDN  <= StatexDP;
    RcntxDN   <= (others => '0');
    TENcntxDN <= (others => '0');
    OUTENxEO  <= '0';
    XOR1xSO   <= '0';

    case StatexDP is
      -------------------------------------------------------------------------
      when idle =>

        if StartxSI = '1' and INENxEI = '1' then
          StatexDN <= round;
          
        end if;

      -------------------------------------------------------------------------
      when round =>

        if RcntxDP = 31 then
          if INENxEI = '0' then
            XOR1xSO  <= '1';
            StatexDN <= fin;
          
          end if;

        else
          RcntxDN <= RcntxDP + 1;
          
        end if;

      -------------------------------------------------------------------------
      when fin =>

        if RcntxDP = 31 then
          if TENcntxDP = 9 then
            OUTENxEO <= '1';
            StatexDN <= idle;

          else
            TENcntxDN <= TENcntxDP + 1;
            
          end if;

        else
          TENcntxDN <= TENcntxDP;
          RcntxDN   <= RcntxDP + 1;
          
        end if;

      -------------------------------------------------------------------------
      when others => StatexDN <= idle;
                     
    end case;
    
  end process p_fsm;

  p_mem : process (ClkxCI, RstxRBI)
  begin  -- process p_mem
    if RstxRBI = '0' then               -- asynchronous reset (active low)
      StatexDP  <= idle;
      RcntxDP   <= (others => '0');
      TENcntxDP <= (others => '0');
      
    elsif ClkxCI'event and ClkxCI = '1' then  -- rising clock edge
      StatexDP  <= StatexDN;
      RcntxDP   <= RcntxDN;
      TENcntxDP <= TENcntxDN;
      
    end if;
  end process p_mem;

end rtl;