#!/bin/csh ############################################################ ## Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich ## http://www.iis.ee.ethz.ch/~sha3 ############################################################ # sample script to run gatelevel simulation with sdf timings # # >>> Adapt it for your design !!! <<< (see README.postlayout) # set VER=6.5a set LIB=gate_slow #vsim-${VER} -c -t 1ps -lib ${LIB} -do "run -all; quit" \ vsim-${VER} -t 1ps -lib ${LIB} \ -L fsd0a_a_generic_core_verilog \ -sdftyp MutInst=../encounter/out/echo_slow.sdf.gz +sdf_verbose \ -v2k_int_delays +no_glitch_msg \ echotb # use: # # vsim-6.4 -help # # to see available options # the results are here cat ../simvectors/echo_simrept.asc