------------------------------------------------------------
-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
use std.textio.all;
library ieee;
use ieee.std_logic_textio.all;  -- read and write overloaded for std_logic
use ieee.std_logic_1164.all;
use work.simulstuff.all;
use work.echoTbPkg.all;
use ieee.numeric_std.all;

-------------------------------------------------------------------------------

entity echoTb is
  -- a testbench does not connect to any higher level of hierarchy
end echoTb;

-------------------------------------------------------------------------------

architecture behavioral of echoTb is

  component echo
    port (
      DataInxDI  : in  std_logic_vector(1535 downto 0);
      LastxSI    : in  std_logic;
      InENxSI    : in  std_logic;
      DataOutxDO : out std_logic_vector(255 downto 0);
      OutEnxSO   : out std_logic;
      CLKxCI     : in  std_logic;
      RSTxRBI    : in  std_logic);
  end component;

  file exprespfile  : text open read_mode is EXPRESP_FILENAME;
  signal InENxS, OutEnxS, RSTxRB : std_logic;

-------------------------------------------------------------------------------
-- BEGIN
-------------------------------------------------------------------------------
begin

  MutInst: echo
    port map (
      DataInxDI  => StimuliRecxD.DataInxD,
      LastxSI    => StimuliRecxD.LastxS,
      InENxSI    => InENxS,
      DataOutxDO => ActResponseRecxD.DataOutxD,
      OutEnxSO   => OutEnxS,
      CLKxCI     => CLKxC,
      RSTxRBI    => RSTxRB);

  

   ClkGen : ClockGenerator(
     ClkxC        => CLKxC,	       
     CLKPHASELOW  => CLK_PHASE_LOW,     
     CLKPHASEHIGH => CLK_PHASE_HIGH );
  
  
    -- obtain stimuli and apply it to MUT
  ----------------------------------------------------------------------------
  StimAppli : process

    -- variables for accounting of mismatching responses
    variable respmatch : respMatchArray;
    variable respaccount : respaccounttype := (0, 0, 0, 0, 0, 0);
    -- variable for counting the lines written to the simulation report
    variable simRepLineCount : natural := 0;

    variable ResponsexD : responseRecordType;

  begin

    -- first the reset phase
    StimuliRecxD.DataInxD <= (others => '0');
    StimuliRecxD.LastxS   <= '0';
    InENxS <= '0';
    
    RSTxRB <= '0';
    wait for 12 ns;
    RSTxRB <= '1';
    
    AppliLoop : while not (endfile(stimulifile)) loop
      wait until CLKxC'event and CLKxC = '1';
      
      -- wait until time has come for stimulus application
      wait for STIMULI_APPLICATION_TIME;
      -- apply stimulus to MUT
      StimuliRecxD <= GetStimuliRecord(stimulifile);      

      -- Also read the response we will check later
      ResponsexD := GetExpectedResponseRecord(exprespfile);
      ExpResponseRecxD.DataOutxD <= ResponsexD.DataOutxD;


      InENxS <= '1';
      -- wait at least a clock
      -- assumes the output will not come in one clock cycle
      -- which for ECHO is true
      wait until CLKxC'event and CLKxC = '1';
      wait for STIMULI_APPLICATION_TIME;
      InENxS <= '0';
      wait for RESPONSE_ACQUISITION_TIME - STIMULI_APPLICATION_TIME;

      RespLoop: while OutEnxS = '0' loop
        wait until CLKxC'event and CLKxC = '1';
        wait for RESPONSE_ACQUISITION_TIME;      
      end loop RespLoop;

          
      -- compare the actual with the expected responses
      CheckResponse(ActResponseRecxD, ExpResponseRecxD,
                       respmatch, respaccount);
        
      -- add a trace line to report file
      PutSimulationReportTrace(simreptfile, StimuliRecxD, ActResponseRecxD,
                                   respmatch, respaccount, simRepLineCount);
        
      -- add extra failure message to report file if necessary
      PutSimulationReportFailure(simreptfile, ExpResponseRecxD, respmatch);

      -- this loop assumes that there is a cycle difference between
      -- data calculation finished and new data applied. The circuit itself
      -- can work faster, however, I was too lazy forthe testbecnh at the
      -- moment. 


    end loop AppliLoop;

    -- when the present clock cycle is the final one of this run
    -- then establish a simulation report summary and write it to file
    PutSimulationReportSummary(simreptfile, respaccount);
    -- close the file
    file_close(simreptfile);
    file_close(exprespfile);
    file_close(stimulifile);
    -- tell clock generator to stop at the end of current cycle
    -- because stimuli have been exhausted
    EndOfSimxS <= true;

    report "Simulation run completed!";
    wait;    

  end process StimAppli;


end architecture behavioral;