------------------------------------------------------------ -- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich -- http://www.iis.ee.ethz.ch/~sha3 ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; entity mixcolumn is port ( InpxDI : in std_logic_vector(31 downto 0); OupxDO : out std_logic_vector(31 downto 0) ); end mixcolumn; architecture structural of mixcolumn is -- Input Data signal DataIn0xD : std_logic_vector(7 downto 0); signal DataIn1xD : std_logic_vector(7 downto 0); signal DataIn2xD : std_logic_vector(7 downto 0); signal DataIn3xD : std_logic_vector(7 downto 0); -- Data after Mulenc signal DataMulenc0xD : std_logic_vector(31 downto 0); signal DataMulenc1xD : std_logic_vector(31 downto 0); signal DataMulenc2xD : std_logic_vector(31 downto 0); signal DataMulenc3xD : std_logic_vector(31 downto 0); -- Data after XOR signal DataOut0xD : std_logic_vector(7 downto 0); signal DataOut1xD : std_logic_vector(7 downto 0); signal DataOut2xD : std_logic_vector(7 downto 0); signal DataOut3xD : std_logic_vector(7 downto 0); component mulenc port ( InpxDI : in std_logic_vector(7 downto 0); OupxDO : out std_logic_vector(31 downto 0) ); end component; begin -- structural DataIn0xD <= InpxDI(31 downto 24); DataIn1xD <= InpxDI(23 downto 16); DataIn2xD <= InpxDI(15 downto 8); DataIn3xD <= InpxDI( 7 downto 0); mulenc0 : mulenc port map ( DataIn0xD, DataMulenc0xD); mulenc1 : mulenc port map ( DataIn1xD, DataMulenc1xD); mulenc2 : mulenc port map ( DataIn2xD, DataMulenc2xD); mulenc3 : mulenc port map ( DataIn3xD, DataMulenc3xD); DataOut0xD <= DataMulenc0xD(23 downto 16) xor DataMulenc1xD(31 downto 24) xor DataMulenc2xD( 7 downto 0) xor DataMulenc3xD( 7 downto 0); DataOut1xD <= DataMulenc0xD( 7 downto 0) xor DataMulenc1xD(23 downto 16) xor DataMulenc2xD(31 downto 24) xor DataMulenc3xD( 7 downto 0); DataOut2xD <= DataMulenc0xD( 7 downto 0) xor DataMulenc1xD( 7 downto 0) xor DataMulenc2xD(23 downto 16) xor DataMulenc3xD(31 downto 24); DataOut3xD <= DataMulenc0xD(31 downto 24) xor DataMulenc1xD( 7 downto 0) xor DataMulenc2xD( 7 downto 0) xor DataMulenc3xD(23 downto 16); OupxDO <= DataOut0xD & DataOut1xD & DataOut2xD & DataOut3xD; end structural;