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-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
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library ieee;
use ieee.std_logic_1164.all;

entity mulenc is
  
  port (
    InpxDI : in  std_logic_vector( 7 downto 0);
    OupxDO : out std_logic_vector(31 downto 0)
    );

end mulenc;


architecture structural of mulenc is
  signal Data0xD     : std_logic_vector(7 downto 0);
  signal Data1xD     : std_logic_vector(7 downto 0);
  signal Data2xD     : std_logic_vector(7 downto 0);
  signal Data3xD     : std_logic_vector(7 downto 0);

  component xtime 
      port (
        InpxDI : in  std_logic_vector(7 downto 0);
        OupxDO : out std_logic_vector(7 downto 0)
      );
  end component;

begin
   Data0xD <= InpxDI;
   Data1xD <= InpxDI;
 
   mul2 : xtime port map (
     InpxDI, Data2xD);

   Data3xD <= InpxDI xor Data2xD;

   OupxDO <= Data3xD & Data2xD & Data1xD & Data0xD;
  
end structural;