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-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
-- http://www.iis.ee.ethz.ch/~sha3
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- for int conversion
entity sbox is
port (
InpxDI : in std_logic_vector(7 downto 0); -- 8 bit unsubstituted data in
OupxDO : out std_logic_vector(7 downto 0) -- 8 bit substituted data out
);
end sbox;
architecture galois of sbox is
component GF256toGF16
port (
inxDI : in std_logic_vector(7 downto 0);
outhxDO : out std_logic_vector(3 downto 0);
outlxDO : out std_logic_vector(3 downto 0));
end component;
component GF256invWolk
port (
InhxDI : in std_logic_vector(3 downto 0);
InlxDI : in std_logic_vector(3 downto 0);
OuthxDO : out std_logic_vector(3 downto 0);
OutlxDO : out std_logic_vector(3 downto 0));
end component;
component GF16toGF256
port (
inlxDI : in std_logic_vector(3 downto 0);
inhxDI : in std_logic_vector(3 downto 0);
outxDO : out std_logic_vector(7 downto 0));
end component;
component GF256affine
port (
inXDI : in std_logic_vector(7 downto 0);
outxDO : out std_logic_vector(7 downto 0));
end component;
component affinetrans
port (
InpxDI : in std_logic_vector(7 downto 0);
OupxDO : out std_logic_vector(7 downto 0));
end component;
signal ah : std_logic_vector(3 downto 0);
signal al : std_logic_vector(3 downto 0);
signal invl : std_logic_vector(3 downto 0);
signal invh : std_logic_vector(3 downto 0);
signal inv : std_logic_vector(7 downto 0);
begin -- SBox8bitRTL
GF256toGF16Inst: GF256toGF16
port map (
inxDI => InpxDI ,
outhxDO => ah,
outlxDO => al);
GF256invWolInst: GF256invWolk
port map (
InhxDI => ah,
InlxDI => al,
OuthxDO => invh,
OutlxDO => invl);
GF16toGF256Inst: GF16toGF256
port map (
inlxDI => invl,
inhxDI => invh,
outxDO => inv);
i_affine: affinetrans
port map (
InpxDI => inv,
OupxDO => OupxDO);
end galois;
library ieee;
use ieee.std_logic_1164.all;
entity GF256toGF16 is
port (
inxDI : in std_logic_vector(7 downto 0);
outhxDO : out std_logic_vector(3 downto 0);
outlxDO : out std_logic_vector(3 downto 0));
end GF256toGF16;
architecture GF256toGF16RTL of GF256toGF16 is
signal intermAxD : std_logic;
signal intermBxD : std_logic;
signal intermCxD : std_logic;
begin -- GF256toGF16RTL
intermAxD <= inxDI(1) xor inxDI(7);
intermBxD <= inxDI(5) xor inxDI(7);
intermCxD <= inxDI(4) xor inxDI(6);
outlxDO(0) <= intermCxD xor inxDI(0) xor inxDI(5);
outlxDO(1) <= inxDI(1) xor inxDI(2);
outlxDO(2) <= intermAxD;
outlxDO(3) <= inxDI(2) xor inxDI(4);
outhxDO(0) <= intermCxD xor inxDI(5);
outhxDO(1) <= intermAxD xor intermCxD;
outhxDO(2) <= intermBxD xor inxDI(2) xor inxDI(3);
outhxDO(3) <= intermBxD;
end GF256toGF16RTL;
library ieee;
use ieee.std_logic_1164.all;
entity GF16toGF256 is
port (
inlxDI : in std_logic_vector(3 downto 0);
inhxDI : in std_logic_vector(3 downto 0);
outxDO : out std_logic_vector(7 downto 0));
end GF16toGF256;
architecture GF16toGF256RTL of GF16toGF256 is
signal intermAxD : std_logic;
signal intermBxD : std_logic;
begin -- GF16toGF256RTL
intermAxD <= inlxDI(1) xor inhxDI(3);
intermBxD <= inhxDI(0) xor inhxDI(1);
outxDO(0) <= inlxDI(0) xor inhxDI(0);
outxDO(1) <= intermBxD xor inhxDI(3);
outxDO(2) <= intermAxD xor intermBxD;
outxDO(3) <= intermBxD xor inlxDI(1) xor inhxDI(2);
outxDO(4) <= intermAxD xor intermBxD xor inlxDI(3);
outxDO(5) <= intermBxD xor inlxDI(2);
outxDO(6) <= intermAxD xor inlxDI(2) xor inlxDI(3) xor inhxDI(0);
outxDO(7) <= intermBxD xor inlxDI(2) xor inhxDI(3);
end GF16toGF256RTL;
library ieee;
use ieee.std_logic_1164.all;
entity GF256invWolk is
port (
InhxDI : in std_logic_vector(3 downto 0);
InlxDI : in std_logic_vector(3 downto 0);
OuthxDO : out std_logic_vector(3 downto 0);
OutlxDO : out std_logic_vector(3 downto 0));
end GF256invWolk;
architecture GF256invWolkRTL of GF256invWolk is
component GF16sqr
port (
inxDI : in std_logic_vector(3 downto 0);
outxDO : out std_logic_vector(3 downto 0));
end component;
component GF16mul_e
port (
inAxDI : in std_logic_vector(3 downto 0);
outxDO : out std_logic_vector(3 downto 0));
end component;
component GF16mul
port (
MulAxDI : in std_logic_vector(3 downto 0);
MulBxDI : in std_logic_vector(3 downto 0);
ProCxDO : out std_logic_vector(3 downto 0));
end component;
component GF16inv
port (
inxDI : in std_logic_vector(3 downto 0);
outxDO : out std_logic_vector(3 downto 0));
end component;
signal ah : std_logic_vector(3 downto 0);
signal al : std_logic_vector(3 downto 0);
signal ah0 : std_logic_vector(3 downto 0);
signal al0 : std_logic_vector(3 downto 0);
signal ah1 : std_logic_vector(3 downto 0);
signal a0 : std_logic_vector(3 downto 0);
signal a1 : std_logic_vector(3 downto 0);
signal a2 : std_logic_vector(3 downto 0);
signal a3 : std_logic_vector(3 downto 0);
signal a4 : std_logic_vector(3 downto 0);
signal a5 : std_logic_vector(3 downto 0);
signal a6 : std_logic_vector(3 downto 0);
begin -- GF256invWolkRTL
ah <= InhxDI;
al <= InlxDI;
GF16sqr0Inst: GF16sqr
port map (
inxDI => ah,
outxDO => ah0);
GF16sqr1Inst: GF16sqr
port map (
inxDI => al,
outxDO => al0);
GF16mul_eInst: GF16mul_e
port map (
inAxDI => ah0,
outxDO => ah1);
a0 <= ah1 xor al0;
GF16mul0Inst: GF16mul
port map (
MulAxDI => ah,
MulBxDI => al,
ProCxDO => a1);
a2 <= a0 xor a1;
GF16invInst: GF16inv
port map (
inxDI => a2,
outxDO => a3);
GF16mul1Inst: GF16mul
port map (
MulAxDI => ah,
MulBxDI => a3,
ProCxDO => a4);
a5 <= ah xor al;
GF16mul2Inst: GF16mul
port map (
MulAxDI => a3,
MulBxDI => a5,
ProCxDO => a6);
OuthxDO <= a4;
OutlxDO <= a6;
end GF256invWolkRTL;
library ieee;
use ieee.std_logic_1164.all;
entity GF16sqr is
port (
inxDI : in std_logic_vector(3 downto 0);
outxDO : out std_logic_vector(3 downto 0));
end GF16sqr;
architecture GF16sqrRTL of GF16sqr is
begin -- GF16sqrRTL
outxDO(0) <= inxDI(0) xor inxDI(2);
outxDO(1) <= inxDI(2);
outxDO(2) <= inxDI(1) xor inxDI(3);
outxDO(3) <= inxDI(3);
end GF16sqrRTL;
library ieee;
use ieee.std_logic_1164.all;
entity GF16mul_e is
port (
inAxDI : in std_logic_vector(3 downto 0);
outxDO : out std_logic_vector(3 downto 0));
end GF16mul_e;
architecture GF16mul_eRTL of GF16mul_e is
begin -- GF16mul_eRTL
outxDO(0) <= inAxDI(1) xor inAxDI(2) xor inAxDI(3);
outxDO(1) <= inAxDI(0) xor inAxDI(1);
outxDO(2) <= inAxDI(0) xor inAxDI(1) xor inAxDI(2);
outxDO(3) <= inAxDI(0) xor inAxDI(1) xor inAxDI(2) xor inAxDI(3);
end GF16mul_eRTL;
library ieee;
use ieee.std_logic_1164.all;
entity GF16mul is
port (
MulAxDI : in std_logic_vector(3 downto 0);
MulBxDI : in std_logic_vector(3 downto 0);
ProCxDO : out std_logic_vector(3 downto 0));
end GF16mul;
architecture GF16mulRTL of GF16mul is
signal IntermAxD : std_logic;
signal IntermBxD : std_logic;
signal IntermCxD : std_logic;
begin -- GF16mulRTL
IntermAxD <= MulAxDI(0) xor MulAxDI(3);
IntermBxD <= MulAxDI(2) xor MulAxDI(3);
IntermCxD <= MulAxDI(1) xor MulAxDI(2);
ProCxDO(0) <= ((MulAxDI(0) and MulBxDI(0)) xor (MulAxDI(3) and MulBxDI(1)) xor
(MulAxDI(2) and MulBxDI(2)) xor (MulAxDI(1) and MulBxDI(3)));
ProCxDO(1) <= ((MulAxDI(1) and MulBxDI(0)) xor (IntermAxD and MulBxDI(1)) xor
(IntermBxD and MulBxDI(2)) xor (IntermCxD and MulBxDI(3)));
ProCxDO(2) <= ((MulAxDI(2) and MulBxDI(0)) xor (MulAxDI(1) and MulBxDI(1)) xor
(IntermAxD and MulBxDI(2)) xor (IntermBxD and MulBxDI(3)));
ProCxDO(3) <= ((MulAxDI(3) and MulBxDI(0)) xor (MulAxDI(2) and MulBxDI(1)) xor
(MulAxDI(1) and MulBxDI(2)) xor (IntermAxD and MulBxDI(3)));
end GF16mulRTL;
library ieee;
use ieee.std_logic_1164.all;
entity GF16inv is
port (
inxDI : in std_logic_vector(3 downto 0);
outxDO : out std_logic_vector(3 downto 0));
end GF16inv;
architecture GF16invRTL of GF16inv is
signal intermAxD : std_logic;
signal intermBxD : std_logic;
signal intermCxD : std_logic;
signal intermDxD : std_logic;
signal intermExD : std_logic;
signal intermFxD : std_logic;
begin -- GF16invRTL
intermAxD <= inxDI(1) xor inxDI(2) xor inxDI(3) xor (inxDI(1) and inxDI(2) and inxDI(3));
intermBxD <= inxDI(0) and inxDI(1);
intermCxD <= inxDI(0) and inxDI(2);
intermDxD <= inxDI(0) and inxDI(3);
intermExD <= inxDI(1) and inxDI(3);
intermFxD <= inxDI(1) and inxDI(2);
outxDO(0) <= intermAxD xor inxDI(0) xor intermCxD xor intermFxD xor (inxDI(0) and inxDI(1) and inxDI(2));
outxDO(1) <= intermBxD xor intermCxD xor intermFxD xor inxDI(3) xor intermExD xor (inxDI(0) and inxDI(1) and inxDI(3));
outxDO(2) <= intermBxD xor inxDI(2) xor intermCxD xor inxDI(3) xor intermDxD xor (inxDI(0) and inxDI(2) and inxDI(3));
outxDO(3) <= intermAxD xor intermDxD xor intermExD xor (inxDI(2) and inxDI(3));
end GF16invRTL;
library ieee;
use ieee.std_logic_1164.all;
entity affinetrans is
port (
InpxDI : in std_logic_vector(7 downto 0);
OupxDO : out std_logic_vector(7 downto 0)
);
end affinetrans;
architecture structural of affinetrans is
signal InpIxD : std_logic_vector(7 downto 0);
begin
InpIxD(0) <= InpxDI(0) xor InpxDI(4) xor InpxDI(5) xor InpxDI(6) xor InpxDI(7);
InpIxD(1) <= InpxDI(0) xor InpxDI(1) xor InpxDI(5) xor InpxDI(6) xor InpxDI(7);
InpIxD(2) <= InpxDI(0) xor InpxDI(1) xor InpxDI(2) xor InpxDI(6) xor InpxDI(7);
InpIxD(3) <= InpxDI(0) xor InpxDI(1) xor InpxDI(2) xor InpxDI(3) xor InpxDI(7);
InpIxD(4) <= InpxDI(0) xor InpxDI(1) xor InpxDI(2) xor InpxDI(3) xor InpxDI(4);
InpIxD(5) <= InpxDI(1) xor InpxDI(2) xor InpxDI(3) xor InpxDI(4) xor InpxDI(5);
InpIxD(6) <= InpxDI(2) xor InpxDI(3) xor InpxDI(4) xor InpxDI(5) xor InpxDI(6);
InpIxD(7) <= InpxDI(3) xor InpxDI(4) xor InpxDI(5) xor InpxDI(6) xor InpxDI(7);
OupxDO <= InpIxD xor "01100011";
end structural;