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-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
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library ieee;
use ieee.std_logic_1164.all;

entity xtime is
  
  port (
    InpxDI : in  std_logic_vector(7 downto 0);
    OupxDO : out std_logic_vector(7 downto 0)
    );

end xtime;


architecture structural of xtime is
  signal DataxD : std_logic_vector(7 downto 0);
begin
  DataxD <= InpxDI(6 downto 0) & '0';

  OupxDO <= DataxD when (InpxDI(7) = '0') else
            (DataxD xor "00011011");
  
end structural;