############################################################
## Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
##            http://www.iis.ee.ethz.ch/~sha3
############################################################
## simple script

# radical clean 
sh rm -rf WORK/*

# Adjust according tothe num CPUs available
# regular machines have just 2. Arinas have 16 !!
set_host_options -max_cores 2

# less radical clean
remove_design -design



## set the targets to be the worst case library to begin with
set target_library [list fsd0a_a_generic_core_ss1p08v125c.db ]
set link_library   [list "*" dw_foundation.sldb fsd0a_a_generic_core_ss1p08v125c.db ]


## you can change the SBOX type by changing the name of the file
## here. sbox_lut is the one with a single lookup table
##       sbox_arith uses the GF2 expansion
analyze -f vhdl { \
        	  ../sourcecode/echo_fast.vhd \
        	  ../sourcecode/doubleAES.vhd \
        	  ../sourcecode/mixcolumn.vhd \
        	  ../sourcecode/mulenc.vhd \
        	  ../sourcecode/sbox_lut.vhd \
        	  ../sourcecode/shiftrows.vhd \
        	  ../sourcecode/xtime.vhd }

########################################################
#### Bottom up compile                            ######
####                                              ######
#### SBOX                                         ######
########################################################
## let us get the SBOX compiled first 
elaborate sbox

## constraints 
  set_driving_cell -no_design_rule  -library fsd0a_a_generic_core_ss1p08v125c -lib_cell BUFX8 [remove_from_collection [all_inputs] ClkxCI]
# simple load
  set_load 0.010 [all_outputs]
## no clock in this design 
# set_max_delay 0.50 -to [all_outputs]
 set_max_delay 0.65 -to [all_outputs]
## this is very easy constraint
## set_max_delay 0.70 -to [all_outputs]
 set_max_area 0
 
 compile_ultra
 set_dont_touch [find design sbox]

 write -f ddc -o DDC/sbox.ddc

# remove_design -design
# read_ddc DDC/sbox.ddc 

########################################################
#### Bottom up compile                            ######
####                                              ######
#### double AES                                   ######
########################################################
elaborate doubleAES

current_design mixcolumn
ungroup -all -flatten
current_design doubleAES
ungroup [find cell i_shiftrows*]

## constraints 
  set_driving_cell -no_design_rule  -library fsd0a_a_generic_core_ss1p08v125c -lib_cell BUFX8 [remove_from_collection [all_inputs] CLKxCI]
# simple load
  set_load 0.010 [all_outputs]
## no clock in this design, this is achievable if the above is ok
# set_max_delay 1.50 -to [all_outputs]
 set_max_delay 2.00 -to [all_outputs]
 set_max_area 0
 
 compile_ultra
 set_dont_touch [find design doubleAES]

 write -f ddc -o DDC/doubleAES.ddc


########################################################
#### Top down compile can start here              ######
####                                              ######
########################################################

elaborate echo

current_design mixcolumn
ungroup -all -flatten
current_design echo


## constraints 
## we need 2.4ns for 20 Gbps
 #set CLK 2.0
## 15 Gbps
 set CLK 3.2
 create_clock -name CLKxCI -period $CLK CLKxCI 
 set_input_delay  0  -clock CLKxCI  [remove_from_collection [all_inputs] CLKxCI]
 set_output_delay 0  -clock CLKxCI  [all_outputs]
 
## driving cell
 set_driving_cell -no_design_rule  -library fsd0a_a_generic_core_ss1p08v125c -lib_cell BUFX8 [remove_from_collection [all_inputs] CLKxCI]
# simple load
 set_load 0.050 [all_outputs]
 set_max_area 0
  
compile_ultra
write_file -h -f ddc -o DDC/echo_fast.ddc
#write_file -h -f ddc -o DDC/echo_fast_bottomup.ddc


## if using a bottom-up compile remove the don't touch and uniquify 
remove_attribute -quiet [find -h design *] dont_touch
uniquify

define_name_rules verilog -add_dummy_nets
change_names -h -rules verilog
write -h -f verilog -o netlists/echo.v
quit