############################################################ ## Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich ## http://www.iis.ee.ethz.ch/~sha3 ############################################################ ## simple script # radical clean sh rm -rf WORK/* # Adjust according tothe num CPUs available # regular machines have just 2. Arinas have 16 !! set_host_options -max_cores 2 # less radical clean remove_design -design ## set the targets to be the worst case library to begin with set target_library [list fsd0a_a_generic_core_ss1p08v125c.db ] set link_library [list "*" dw_foundation.sldb fsd0a_a_generic_core_ss1p08v125c.db ] ## you can change the SBOX type by changing the name of the file ## here. sbox_lut is the one with a single lookup table ## sbox_arith uses the GF2 expansion analyze -f vhdl { \ ../sourcecode/echo_slow.vhd \ ../sourcecode/mixcolumn.vhd \ ../sourcecode/mulenc.vhd \ ../sourcecode/sbox_arith.vhd \ ../sourcecode/xtime.vhd } ######################################################## #### Top down compile can start here ###### #### ###### ######################################################## elaborate echo current_design mixcolumn ungroup -all -flatten current_design sbox ungroup -all -flatten current_design echo ## constraints ## we need 7.42ns for 0.20 Gbps ## 200.000.000 /1536 == 130208 msg/sec ## 1034 cycles/msg ## 134'635'416 cycles per second ## 7.42 ns per cycle ## 15 Gbps set CLK 7 create_clock -name CLKxCI -period $CLK CLKxCI set_input_delay 0 -clock CLKxCI [remove_from_collection [all_inputs] CLKxCI] set_output_delay 0 -clock CLKxCI [all_outputs] ## driving cell set_driving_cell -no_design_rule -library fsd0a_a_generic_core_ss1p08v125c -lib_cell BUFX8 [remove_from_collection [all_inputs] CLKxCI] # simple load set_load 0.050 [all_outputs] set_max_area 0 compile_ultra write_file -h -f ddc -o DDC/echo_slow.ddc #write_file -h -f ddc -o DDC/echo_fast_bottomup.ddc ## if using a bottom-up compile remove the don't touch and uniquify remove_attribute -quiet [find -h design *] dont_touch uniquify define_name_rules verilog -add_dummy_nets change_names -h -rules verilog write -h -f verilog -o netlists/echo_slow.v quit