------------------------------------------------------------
-- Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Title      : Blake controller
-- Project    : Shabziger
-------------------------------------------------------------------------------
-- File       : controller_2G.vhd
-- Author     : Beat Muheim  
-- Company    : Integrated Systems Laboratory, ETH Zurich
-- Created    : 2011-09-15
-- Last update: 2011-09-15
-- Platform   : ModelSim (simulation), Synopsys (synthesis)
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: Blake controller for 2G original by Luca Henzen
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2011-09-15  1.0      bm	Copy from controller.vhd adaptet to 2G
-- 2011-09-16  2.0      bm	for  new ethz_blake
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use work.blakePkg.all;

entity controller is
  port (
    CLKxCI         : in  std_logic;
    RSTxRBI        : in  std_logic;
    VALIDINxSI     : in  std_logic;
    FinBlockxSI    : in  std_logic;
    VALIDOUTxSO    : out std_logic;
    NewMsgxSO      : out std_logic;
    NewBlockSO     : out std_logic;
    PenUltCyclexSO : out std_logic;
    ICNTxSO        : out unsigned(3 downto 0);
    ROUNDxSO       : out unsigned(3 downto 0)
    );

end controller;

architecture hash of controller is

  type state is (idle, round, ready, fin);

  signal STATExDP, STATExDN : state;

  signal ROUNDxDP, ROUNDxDN : unsigned(3 downto 0);
  signal ICNTxDP, ICNTxDN   : unsigned(3 downto 0);

  signal FinBlockxS, FinBlockxSP, FinBlockxSN : std_logic;


begin  -- hash

  ROUNDxSO <= ROUNDxDP;
  ICNTxSO  <= ICNTxDP;

  fsm: process (ICNTxDP, ROUNDxDP, STATExDP, VALIDINxSI, FinBlockxSI, FinBlockxSP)
  begin  -- process fsm
    
    VALIDOUTxSO <= '0';
    
    ROUNDxDN    <= (others => '0');
    ICNTxDN     <= (others => '0');

    PenUltCyclexSO <= '0';
    NewMsgxSO      <= '0';
    NewBlockSO     <= '0';

    FinBlockxSN    <= FinBlockxSP;

    case STATExDP is

      -------------------------------------------------------------------------
      when idle => 

        if VALIDINxSI = '1' then
          FinBlockxSN <= FinBlockxSI;
          NewMsgxSO   <= '1';
          NewBlockSO  <= '1';
          STATExDN <= round;

        else
          STATExDN <= idle;
          
        end if;

      -------------------------------------------------------------------------
      when round => 

        if ROUNDxDP < NROUND-1 then
          if ICNTxDP = 3 then
            ROUNDxDN <= ROUNDxDP + 1;
            STATExDN <= round;

          else
            ROUNDxDN <= ROUNDxDP;
            ICNTxDN  <= ICNTxDP + 1;
            STATExDN <= round;
            
          end if;
          
        else
          if ICNTxDP = 3 then
            PenUltCyclexSO <= '1';
            if FinBlockxSP = '1' then
              STATExDN <= fin;
            else
              STATExDN <= ready;
            end if;
 
          else
            ROUNDxDN <= ROUNDxDP;
            ICNTxDN  <= ICNTxDP + 1;
            STATExDN <= round;
            
          end if;
        end if;

      -------------------------------------------------------------------------
      when ready =>
        
        if VALIDINxSI = '1' then
          NewBlockSO  <= '1';
          FinBlockxSN <= FinBlockxSI;
          StatexDN    <= round;
        else
          StatexDN <= ready;
        end if;
      -------------------------------------------------------------------------
      when fin =>

        VALIDOUTxSO <= '1';
        if VALIDINxSI = '1' then
          FinBlockxSN <= FinBlockxSI;
          NewMsgxSO   <= '1';
          NewBlockSO  <= '1';
          STATExDN    <= round;
        else
          STATExDN <= idle;
          
        end if;

      -------------------------------------------------------------------------
      when others =>

        STATExDN <= idle;
      
    end case;
    
  end process fsm;
  
  
  process (CLKxCI, RSTxRBI)
  begin  -- process
    if RSTxRBI = '0' then               -- asynchronous reset (active low)
      STATExDP <= idle;
      ROUNDxDP <= (others => '0');
      ICNTxDP  <= (others => '0');
      FinBlockxSP  <= '1';
      
    elsif CLKxCI'event and CLKxCI = '1' then  -- rising clock edge
      STATExDP <= STATExDN;
      ROUNDxDP <= ROUNDxDN;
      ICNTxDP  <= ICNTxDN;
      FinBlockxSP <= FinBlockxSN;
       
    end if;
  end process;
  
end hash;