------------------------------------------------------------
-- Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Title      : Blake wrapper
-- Project    : Shabziger
-------------------------------------------------------------------------------
-- File       : ethz_blake.vhd
-- Author     : Beat Muheim  
-- Company    : Integrated Systems Laboratory, ETH Zurich
-- Created    : 2011-08-16
-- Last update: 2011-09-16
-- Platform   : ModelSim (simulation), Synopsys (synthesis)
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: top of blake
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2011-08-15  1.0      bm	Creat
-- 2011-08-23  1.1      bm	renamed TxD->MsgLenxD, INENxE->InWrEnxS
--                              OUTENxE->OutWrEnxS
-- 2011-08-23  1.2	bm	Fix OutWrEnxSO tosynopsys/scripts/blake.tcl flag correct on the end.
-- 2011-08-30  1.3	bm	Change signals to mixed letter.
-- 2011-09-16  2.0	bm	New ethz_blake: combine ethz_blake and black in one
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use work.blakePkg.all;

entity ethz_blake is
  port (
    ClkxCI         : in  std_logic;
    RstxRBI        : in  std_logic;
    ScanInxTI      : in  std_logic;
    ScanOutxTO     : out std_logic;
    ScanEnxTI      : in  std_logic;
    MxDI           : in  std_logic_vector(511 downto 0);
    SxDI           : in  std_logic_vector(127 downto 0);
    MsgLenxDI      : in  std_logic_vector( 63 downto 0);
    HxDO           : out std_logic_vector(255 downto 0);
    FinBlockxSI    : in  std_logic;
    PenUltCyclexSO : out std_logic;
    InWrEnxSI      : in  std_logic;
    OutWrEnxSO     : out std_logic
    );

end ethz_blake;

architecture top of ethz_blake is

  component controller
    port (
      CLKxCI         : in  std_logic;
      RSTxRBI        : in  std_logic;
      VALIDINxSI     : in  std_logic;
      FinBlockxSI    : in  std_logic;
      VALIDOUTxSO    : out std_logic;
      NewMsgxSO      : out std_logic;
      NewBlockSO     : out std_logic;
      PenUltCyclexSO : out std_logic;
      ICNTxSO        : out unsigned(3 downto 0);
      ROUNDxSO       : out unsigned(3 downto 0)
      );
  end component;

  component initialization
    port (
      HxDI : in  std_logic_vector(WWIDTH*8-1 downto 0);
      SxDI : in  std_logic_vector(WWIDTH*4-1 downto 0);
      TxDI : in  std_logic_vector(WWIDTH*2-1 downto 0);
      VxDO : out std_logic_vector(WWIDTH*16-1 downto 0)
      );
  end component;

  component roundreg
    port (
      CLKxCI   : in  std_logic;
      RSTxRBI  : in  std_logic;
      WEIxSI   : in  std_logic;
      ICNTxSI  : in  unsigned(3 downto 0);
      ROUNDxSI : in  unsigned(3 downto 0);
      VxDI     : in  std_logic_vector(WWIDTH*16-1 downto 0);
      MxDI     : in  std_logic_vector(WWIDTH*16-1 downto 0);
      VxDO     : out std_logic_vector(WWIDTH*16-1 downto 0)
      );
  end component;

  component finalization
    port (
      VxDI : in  std_logic_vector(WWIDTH*16-1 downto 0);
      HxDI : in  std_logic_vector(WWIDTH*8-1 downto 0);
      SxDI : in  std_logic_vector(WWIDTH*4-1 downto 0);
      HxDO : out std_logic_vector(WWIDTH*8-1 downto 0)
      );
  end component;

  signal ICNTxS                         : unsigned(3 downto 0);
  signal ROUNDxS                        : unsigned(3 downto 0);
  signal VxD, VFINALxD                  : std_logic_vector(WWIDTH*16-1 downto 0);
  signal VALIDOUTxS                     : std_logic;
  signal NewMsgxS                       : std_logic;
  signal NewBlockS                      : std_logic;
  signal OutHxD, InHxD, HxD, HxDP, HxDN : std_logic_vector(WWIDTH*8-1  downto 0);
  signal MxD, MxDP, MxDN                : std_logic_vector(WWIDTH*16-1 downto 0);

begin  --top
  
  -----------------------------------------------------------------------------
  -- CONTROLLER
  -----------------------------------------------------------------------------
  u_controller: controller
    port map (
      CLKxCI         => CLKxCI,
      RSTxRBI        => RSTxRBI,
      VALIDINxSI     => InWrEnxSI,
      FinBlockxSI    => FinBlockxSI,
      VALIDOUTxSO    => VALIDOUTxS,
      NewMsgxSO      => NewMsgxS,
      NewBlockSO     => NewBlockS,
      PenUltCyclexSO => PenUltCyclexSO,
      ICNTxSO        => ICNTxS,
      ROUNDxSO       => ROUNDxS
      );
  
  -----------------------------------------------------------------------------
  -- INITIALIZATION
  -----------------------------------------------------------------------------
  u_initialization : initialization
    port map (
      HxDI => InHxD,
      SxDI => SxDI,
      TxDI => MsgLenxDI,
      VxDO => VxD
      );

  -----------------------------------------------------------------------------
  -- ROUND
  -----------------------------------------------------------------------------
  u_roundreg: roundreg
    port map (
      CLKxCI   => CLKxCI,
      RSTxRBI  => RSTxRBI,
      WEIxSI   => InWrEnxSI,
      ICNTxSI  => ICNTxS,
      ROUNDxSI => ROUNDxS,
      VxDI     => VxD,
      MxDI     => MxD,
      VxDO     => VFINALxD
      );

  -----------------------------------------------------------------------------
  -- FINALIZATION
  -----------------------------------------------------------------------------
  u_finalization : finalization
    port map (
      VxDI  => VFINALxD,
      HxDI  => HxD,
      SxDI  => SxDI,
      HxDO  => OutHxD
      );
 
  -----------------------------------------------------------------------------
  -- 
  -----------------------------------------------------------------------------
  HxDO       <= OutHxD;
  OutWrEnxSO <= VALIDOUTxS;
  -----------------------------------------------------------------------------
  -- 
  -----------------------------------------------------------------------------
  MxDN  <= MxDI        when NewBlockS = '1' else
           MxDP;
  InHxD <= IV          when NewMsgxS = '1' and NewBlockS = '1' else
           OutHxD;
  HxDN  <= IV          when NewMsgxS = '1' and NewBlockS = '1' else
           OutHxD      when NewMsgxS = '0' and NewBlockS = '1' else
           HxDP;

  HxDO  <= OutHxD;
  HxD   <= HxDP;
  MxD   <= MxDP;

  -----------------------------------------------------------------------------
  p_mem: process (ClkxCI, RstxRBI)
  begin  -- process p_mem
    if RstxRBI = '0' then               -- asynchronous reset (active low)
      MxDP <= (others => '0');
      HxDP <= (others => '0');
    
    elsif ClkxCI'event and ClkxCI = '1' then  -- rising clock edge
      MxDP <= MxDN;
      HxDP <= HxDN;
      
    end if;
  end process p_mem;
 
end top;