------------------------------------------------------------ -- Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich -- http://www.iis.ee.ethz.ch/~sha3 ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Title : roundreg_2G -- Project : Shabziger ------------------------------------------------------------------------------- -- File : roundreg_2G.vhd -- Author : Beat Muheim -- Company : Integrated Systems Laboratory, ETH Zurich -- Created : 2011-09-16 -- Last update: 2011-09-16 -- Platform : ModelSim (simulation), Synopsys (synthesis) -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- Description: Blake roundreg original by Luca Henzen ------------------------------------------------------------------------------- -- Copyright (c) 2011 Integrated Systems Laboratory, ETH Zurich ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2011-09-16 1.0 bm Copy from roundreg.vhd, mod for using 2G. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use std.textio.all; use ieee.std_logic_textio.all; use work.blakePkg.all; entity roundreg is port ( CLKxCI : in std_logic; RSTxRBI : in std_logic; WEIxSI : in std_logic; ICNTxSI : in unsigned(3 downto 0); ROUNDxSI : in unsigned(3 downto 0); VxDI : in std_logic_vector(WWIDTH*16-1 downto 0); MxDI : in std_logic_vector(WWIDTH*16-1 downto 0); VxDO : out std_logic_vector(WWIDTH*16-1 downto 0) ); end roundreg; architecture hash of roundreg is component gcomp port ( AxDI : in std_logic_vector(WWIDTH-1 downto 0); BxDI : in std_logic_vector(WWIDTH-1 downto 0); CxDI : in std_logic_vector(WWIDTH-1 downto 0); DxDI : in std_logic_vector(WWIDTH-1 downto 0); MxDI : in std_logic_vector(WWIDTH*2-1 downto 0); KxDI : in std_logic_vector(WWIDTH*2-1 downto 0); AxDO : out std_logic_vector(WWIDTH-1 downto 0); BxDO : out std_logic_vector(WWIDTH-1 downto 0); CxDO : out std_logic_vector(WWIDTH-1 downto 0); DxDO : out std_logic_vector(WWIDTH-1 downto 0) ); end component; type SUBT16 is array (15 downto 0) of std_logic_vector(WWIDTH-1 downto 0); signal VxDN, VxDP, MxD : SUBT16; signal G0MxD, G0KxD : std_logic_vector(WWIDTH*2-1 downto 0); signal G1MxD, G1KxD : std_logic_vector(WWIDTH*2-1 downto 0); signal G0AxD, G0BxD, G0CxD, G0DxD : std_logic_vector(WWIDTH-1 downto 0); signal G1AxD, G1BxD, G1CxD, G1DxD : std_logic_vector(WWIDTH-1 downto 0); signal G0AOxD, G0BOxD, G0COxD, G0DOxD : std_logic_vector(WWIDTH-1 downto 0); signal G1AOxD, G1BOxD, G1COxD, G1DOxD : std_logic_vector(WWIDTH-1 downto 0); begin -- hash p_unform: for i in 15 downto 0 generate MxD(15-i) <= MxDI(WWIDTH*(i+1)-1 downto WWIDTH*i); end generate p_unform; VxDO <= VxDP(0) & VxDP(1) & VxDP(2) & VxDP(3) & VxDP(4) & VxDP(5) & VxDP(6) & VxDP(7) & VxDP(8) & VxDP(9) & VxDP(10) & VxDP(11) & VxDP(12) & VxDP(13) & VxDP(14) & VxDP(15); ----------------------------------------------------------------------------- -- MEMORY INPUTS ----------------------------------------------------------------------------- p_inmem: process (G0AOxD, G0BOxD, G0COxD, G0DOxD, G1AOxD, G1BOxD, G1COxD, G1DOxD, VxDI, VxDP, WEIxSI, ICNTxSI) variable IMATRIX_IND : integer; begin -- process p_inmem IMATRIX_IND := (to_integer(ICNTxSI)*2); VxDN <= VxDP; if WEIxSI = '1' then for i in 15 downto 0 loop VxDN(15-i) <= VxDI(WWIDTH*(i+1)-1 downto WWIDTH*i); end loop; else VxDN(IMATRIX(IMATRIX_IND, 0)) <= G0AOxD; VxDN(IMATRIX(IMATRIX_IND, 1)) <= G0BOxD; VxDN(IMATRIX(IMATRIX_IND, 2)) <= G0COxD; VxDN(IMATRIX(IMATRIX_IND, 3)) <= G0DOxD; VxDN(IMATRIX(IMATRIX_IND+1, 0)) <= G1AOxD; VxDN(IMATRIX(IMATRIX_IND+1, 1)) <= G1BOxD; VxDN(IMATRIX(IMATRIX_IND+1, 2)) <= G1COxD; VxDN(IMATRIX(IMATRIX_IND+1, 3)) <= G1DOxD; end if; end process p_inmem; ----------------------------------------------------------------------------- -- G INPUTS ----------------------------------------------------------------------------- p_outmem: process (ICNTxSI, MxD, ROUNDxSI, VxDP) variable IMATRIX_IND : integer; variable PMATRIX_IND : integer; variable ICNTxS : integer; begin -- process p_outmem IMATRIX_IND := to_integer(ICNTxSI)*2; PMATRIX_IND := (to_integer(ROUNDxSI))mod 10; ICNTxS := to_integer(ICNTxSI); G0AxD <= VxDP(IMATRIX(IMATRIX_IND, 0)); G0BxD <= VxDP(IMATRIX(IMATRIX_IND, 1)); G0CxD <= VxDP(IMATRIX(IMATRIX_IND, 2)); G0DxD <= VxDP(IMATRIX(IMATRIX_IND, 3)); G0MxD <= MxD(PMATRIX(PMATRIX_IND, ICNTxS*4)) & MxD(PMATRIX(PMATRIX_IND, ICNTxS*4+1)); G0KxD <= C(PMATRIX(PMATRIX_IND, ICNTxS*4+1)) & C(PMATRIX(PMATRIX_IND, ICNTxS*4)); G1AxD <= VxDP(IMATRIX(IMATRIX_IND+1, 0)); G1BxD <= VxDP(IMATRIX(IMATRIX_IND+1, 1)); G1CxD <= VxDP(IMATRIX(IMATRIX_IND+1, 2)); G1DxD <= VxDP(IMATRIX(IMATRIX_IND+1, 3)); G1MxD <= MxD(PMATRIX(PMATRIX_IND, ICNTxS*4+2)) & MxD(PMATRIX(PMATRIX_IND, ICNTxS*4+3)); G1KxD <= C(PMATRIX(PMATRIX_IND, ICNTxS*4+3)) & C(PMATRIX(PMATRIX_IND, ICNTxS*4+2)); end process p_outmem; ----------------------------------------------------------------------------- -- G BLOCK ----------------------------------------------------------------------------- u_gcomp0: gcomp port map ( AxDI => G0AxD, BxDI => G0BxD, CxDI => G0CxD, DxDI => G0DxD, MxDI => G0MxD, KxDI => G0KxD, AxDO => G0AOxD, BxDO => G0BOxD, CxDO => G0COxD, DxDO => G0DOxD ); u_gcomp1: gcomp port map ( AxDI => G1AxD, BxDI => G1BxD, CxDI => G1CxD, DxDI => G1DxD, MxDI => G1MxD, KxDI => G1KxD, AxDO => G1AOxD, BxDO => G1BOxD, CxDO => G1COxD, DxDO => G1DOxD ); ----------------------------------------------------------------------------- -- V MEMORY ----------------------------------------------------------------------------- p_mem: process (CLKxCI, RSTxRBI) begin -- process p_vmem if RSTxRBI = '0' then -- asynchronous reset (active low) VxDP <= (others => (others => '0')); elsif CLKxCI'event and CLKxCI = '1' then -- rising clock edge VxDP <= VxDN; end if; end process p_mem; end hash;