------------------------------------------------------------
-- Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Title      : One row of Mixbytes
-- Project    : Shabziger
-------------------------------------------------------------------------------
-- File       : g_mixbytes.vhd
-- Author     : Frank K. Guerkaynak  
-- Company    : Integrated Systems Laboratory, ETH Zurich
-- Created    : 2011-08-21
-- Last update: 2011-09-03
-- Platform   : ModelSim (simulation), Synopsys (synthesis)
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: This is 1/8th of the Mixbytes operation
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2011-08-21  1.0      kgf	Code copied from groestl code from the SHA2
--                              implementations.
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity g_mixbytes is
  
  port (
    InxDI  : in  std_logic_vector(63 downto 0);
    OutxDO : out std_logic_vector(7 downto 0));

end g_mixbytes;

architecture rtl of g_mixbytes is


 type statearray  is array (0 to 7) of std_logic_vector (7 downto 0);
 signal DxD : statearray;               -- ease of programming
 -- result of each column 
 signal C1xD, C2xD, C3xD, C4xD, C5xD, C6xD, C7xD, C8xD : std_logic_vector(7 downto 0);
 -- helping signals for complex columns 
 signal C41xD, C51xD, C71xD, C81xD : std_logic_vector(7 downto 0);
 
begin  -- rtl
  
 -- copy the input into the state array
 -- we assume that the first element of the row is at the MSB
 -- and the least significant on the LSB
  gen_in: for i in 0 to 7 generate
    DxD(i) <= InxDI( (7-i)*8 + 7 downto (7-i)*8);
  end generate gen_in;

-- multiply each column with entries of the row
    -- x 02 
    C1xD  <=      DxD(0)(6 downto 0)&'0' when DxD(0)(7) = '0'
             else DxD(0)(6 downto 0)&'0' xor x"1b";

    -- x 02
    C2xD  <=      DxD(1)(6 downto 0)&'0' when DxD(1)(7) = '0'
             else DxD(1)(6 downto 0)&'0' xor x"1b";

    -- x 03
    C3xD  <=       (DxD(2)(6 downto 0)&'0') xor DxD(2)  when DxD(2)(7) = '0'
             else ((DxD(2)(6 downto 0)&'0') xor DxD(2)) xor x"1b";

    -- x 04
    C41xD  <= DxD(3)(5 downto 0)&'0'&'0';
    C4xD   <=      C41xD           when DxD(3)(7) = '0' and DxD(3)(6) = '0'
              else C41xD xor x"36" when DxD(3)(7) = '1' and DxD(3)(6) = '0'
              else C41xD xor x"1b" when DxD(3)(7) = '0' and DxD(3)(6) = '1'
              else C41xD xor x"2d";

    -- x 05
    C51xD  <= (DxD(4)(5 downto 0)&'0'&'0') xor DxD(4);
    C5xD   <=      C51xD when DxD(4)(7) = '0' and DxD(4)(6) = '0'
              else C51xD xor x"36" when DxD(4)(7) = '1' and DxD(4)(6) = '0'
              else C51xD xor x"1b" when DxD(4)(7) = '0' and DxD(4)(6) = '1'
              else C51xD xor x"2d";

    -- x 03
    C6xD  <=       (DxD(5)(6 downto 0)&'0') xor DxD(5) when DxD(5)(7) = '0'
             else ((DxD(5)(6 downto 0)&'0') xor DxD(5)) xor x"1b";

    -- x 05
    C71xD  <= DxD((6))(5 downto 0)&'0'&'0' xor DxD(6);
    C7xD   <=      C71xD when DxD(6)(7) = '0' and DxD(6)(6) = '0'
              else C71xD xor x"36" when DxD(6)(7) = '1' and DxD(6)(6) = '0'
              else C71xD xor x"1b" when DxD(6)(7) = '0' and DxD(6)(6) = '1'
              else C71xD xor x"2d";

    -- x 07
    C81xD  <= (DxD(7)(6 downto 0)&'0') xor (DxD(7)(5 downto 0)&'0'&'0') xor DxD(7);
    C8xD   <=      C81xD when DxD(7)(7) = '0' and DxD(7)(6) = '0'
              else C81xD xor x"2d" when DxD(7)(7) = '1' and DxD(7)(6) = '0'
              else C81xD xor x"1b" when DxD(7)(7) = '0' and DxD(7)(6) = '1'
              else C81xD xor x"36";

-- Determine the output
 OutxDO <= C1xD xor C2xD xor C3xD xor C4xD xor
           C5xD xor C6xD xor C7xD xor C8xD;



end rtl;