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-- Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity gf4map_2 is
  port (
    AxDI  : in  std_logic_vector(7 downto 0);
    AhxDO : out std_logic_vector(3 downto 0);
    AlxDO : out std_logic_vector(3 downto 0));

end gf4map_2;

architecture rtl of gf4map_2 is

  signal AAxD : std_logic;
  signal ABxD : std_logic;
  signal ACxD : std_logic;
    
begin  -- rtl

  AAxD <= AxDI(1) xor AxDI(7);
  ABxD <= AxDI(5) xor AxDI(7);
  ACxD <= AxDI(4) xor AxDI(6);
    
  AhxDO(0) <= ACxD xor AxDI(5);
  AhxDO(1) <= AAxD xor ACxD;
  AhxDO(2) <= ABxD xor AxDI(2) xor AxDI(3);
  AhxDO(3) <= ABxD;
  AlxDO(0) <= ACxD xor AxDI(0) xor AxDI(5);
  AlxDO(1) <= AxDI(1) xor AxDI(2);
  AlxDO(2) <= AAxD;
  AlxDO(3) <= AxDI(2) xor AxDI(4);  
    
end rtl;