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-- Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity gf4mult_2 is
  port (
    AxDI : in  std_logic_vector(3 downto 0);
    BxDI : in  std_logic_vector(3 downto 0);
    CxDO : out std_logic_vector(3 downto 0));

end gf4mult_2;

architecture rtl of gf4mult_2 is
  
  signal AAxD : std_logic;
  signal ABxD : std_logic;
  
begin  -- rtl

  AAxD <= AxDI(0) xor AxDI(3);
  ABxD <= AxDI(2) xor AxDI(3);

  CxDO(0) <= (AxDI(0) and BxDI(0)) xor (AxDI(3) and BxDI(1)) xor (AxDI(2) and BxDI(2)) xor (AxDI(1) and BxDI(3));
  CxDO(1) <= (AxDI(1) and BxDI(0)) xor (AAxD and BxDI(1)) xor (ABxD and BxDI(2)) xor ((AxDI(1) xor AxDI(2)) and BxDI(3));
  CxDO(2) <= (AxDI(2) and BxDI(0)) xor (AxDI(1) and BxDI(1)) xor (AAxD and BxDI(2)) xor (ABxD and BxDI(3));
  CxDO(3) <= (AxDI(3) and BxDI(0)) xor (AxDI(2) and BxDI(1)) xor (AxDI(1) and BxDI(2)) xor (AAxD and BxDI(3));
  
end rtl;