------------------------------------------------------------ -- Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich -- http://www.iis.ee.ethz.ch/~sha3 ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Title : Sub Bytes using GF2 decomposition -- Project : Shabziger ------------------------------------------------------------------------------- -- File : groestl_subbytes.vhd -- Author : Frank K. Guerkaynak -- Company : Integrated Systems Laboratory, ETH Zurich -- Created : 2011-08-21 -- Last update: 2011-09-02 -- Platform : ModelSim (simulation), Synopsys (synthesis) -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- Description: Taken from SHA3r2 Groestl as it is ------------------------------------------------------------------------------- -- Copyright (c) 2011 Integrated Systems Laboratory, ETH Zurich ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2011-08-21 1.0 kgf Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity groestl_subbytes is port ( DxDI : in std_logic_vector(7 downto 0); DxDO : out std_logic_vector(7 downto 0)); end groestl_subbytes; architecture rtl of groestl_subbytes is component gf4map_2 port ( AxDI : in std_logic_vector(7 downto 0); AhxDO : out std_logic_vector(3 downto 0); AlxDO : out std_logic_vector(3 downto 0)); end component; component gf4sqr_2 port ( AxDI : in std_logic_vector(3 downto 0); A2xDO : out std_logic_vector(3 downto 0)); end component; component gf4inv_2 port ( AxDI : in std_logic_vector(3 downto 0); AInvxDO : out std_logic_vector(3 downto 0)); end component; component gf4mult_2 port ( AxDI : in std_logic_vector(3 downto 0); BxDI : in std_logic_vector(3 downto 0); CxDO : out std_logic_vector(3 downto 0)); end component; component gf4imapaffine_2 port ( AhxDI : in std_logic_vector(3 downto 0); AlxDI : in std_logic_vector(3 downto 0); AxDO : out std_logic_vector(7 downto 0)); end component; signal AhxD, AlxD : std_logic_vector(3 downto 0); signal Ah2xD, Al2xD : std_logic_vector(3 downto 0); signal AmxD, ApxD : std_logic_vector(3 downto 0); signal AexD, Ael2pxD, AppxD, AinvxD : std_logic_vector(3 downto 0); signal AhsxD, AlsxD : std_logic_vector(3 downto 0); begin -- rtl u_gf4map2: gf4map_2 port map ( AxDI => DxDI, AhxDO => AhxD, AlxDO => AlxD); u_gf4sqr_h2: gf4sqr_2 port map ( AxDI => AhxD, A2xDO => Ah2xD); u_gf4sqr_l2: gf4sqr_2 port map ( AxDI => AlxD, A2xDO => Al2xD); u_gf4mult_e2: gf4mult_2 port map ( AxDI => Ah2xD, BxDI => "1110", CxDO => AexD); u_gf4mult2: gf4mult_2 port map ( AxDI => AlxD, BxDI => AhxD, CxDO => AmxD); ApxD <= AlxD xor AhxD; Ael2pxD <= AexD xor Al2xD; AppxD <= Ael2pxD xor AmxD; u_gf4inv2: gf4inv_2 port map ( AxDI => AppxD, AInvxDO => AinvxD); u_gf4mult_h2: gf4mult_2 port map ( AxDI => AhxD, BxDI => AinvxD, CxDO => AhsxD); u_gf4mult_l2: gf4mult_2 port map ( AxDI => AinvxD, BxDI => ApxD, CxDO => AlsxD); u_gf4imapaffine2: gf4imapaffine_2 port map ( AhxDI => AhsxD, AlxDI => AlsxD, AxDO => DxDO); end rtl;