############################################################
## Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich
##            http://www.iis.ee.ethz.ch/~sha3
############################################################
# Groestl is faster if we elaborate things separately 


## Compile SUBBYTES ------------------------------------------------------
current_design groestl_subbytes

# some dummy constraints
set_load [load_of ${LIB}/${LOAD_CELL}/${LOAD_PIN}] [all_outputs]
set_driving_cell -no_design_rule -library ${LIB} -lib_cell ${DRIV_CELL} -pin ${DRIV_PIN} [all_inputs]

# this should be common 
if  {[llength $CLOCKLIST] == 1 } {
  set_wire_load_model -library shabziger_chip_flat -name groestl_subbytes_0.top.i_ethz_groestl.i_p.i_subbytes_0_flat
}
# one fourth of the total period for subbytes.. harsh.. 
set subbytesdelay [expr $CLOCK/4] 
set_max_delay $subbytesdelay -to [all_outputs]

compile_ultra
set_dont_touch [find design groestl_sub*] true

## Compile TOP with SUBBytes dont touched --------------------------------
current_design ethz_groestl
compile_ultra -scan


## Uniquify and remove dont_touch ----------------------------------------

remove_attribute [find design groestl_sub*] dont_touch
current_design groestl_p
uniquify -cell [get_cells *sub*]

current_design groestl_q
uniquify -cell [get_cells *sub*]


# reset the wireload.. don't know if this is necessary
#if  {[llength $CLOCKLIST] == 1 } {
  foreach NUM {0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15} {
    current_design groestl_subbytes_${NUM}
    ## this is an SBOX the wireload should be the same 
    set_wire_load_model -library shabziger_chip_flat -name groestl_subbytes_15.top.i_ethz_groestl.i_p.i_subbytes_0_flat
  }
#}

## Incremental compile --------------------------------------------------

current_design ethz_groestl
compile_ultra -incremental