------------------------------------------------------------
-- Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Title      : FSM for jh 256
-- Project    : shabziger
-------------------------------------------------------------------------------
-- File       : jhfsm_con.vhd
-- Author     : Beat Muheim  
-- Company    : Integrated Systems Laboratory, ETH Zurich
-- Created    : 2011-08-19
-- Last update: 2011-09-03
-- Platform   : ModelSim (simulation), Synopsys (synthesis)
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: FSM for jh 256 (for jh_con.vhd, jh_comb.vhd) original writen by 
--              Patrice Guillet, Enrico Pargaetzi and Martin Zollerf
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2011-08-19  1.0      bm	created
-- 2011-09-02  1.1      bm      change a lot the state machine
-- 2011-09-03  1.2      kgf     hacked the statemachine a little bit
-- 2011-09-10  1.3	bm	make it work output -> round without idle state
--                              removed Rlast, add NewBlockSO
--				take out "if TENcntxDP < NROUND - 1"
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity JFSM is

  port (
    ClkxCI         : in  std_logic;
    RstxRBI        : in  std_logic;
    InWrEnxSI      : in  std_logic;
    FinBlockxSI    : in  std_logic;
    CntxDO         : out unsigned(7 downto 0);
    SavexSO        : out std_logic;
    NewMsgxSO      : out std_logic;
    NewBlockSO     : out std_logic;
    PenUltCyclexSO : out std_logic;
    OutWrEnxSO     : out std_logic);

end JFSM;

architecture rtl of JFSM is

  type   state is (idle, round, ready, output);
  signal StatexDP, StatexDN   : state;
  signal TENcntxDP, TENcntxDN : unsigned(7 downto 0);
  signal FinBlockxSP, FinBlockxSN : std_logic;

  constant NROUND             : integer := 42;      -- ROUND NUMBER
  
begin  -- rtl

  p_fsm : process (InWrEnxSI, StatexDP, TENcntxDP, FinBlockxSP, FinBlockxSI)
  begin  -- process p_fsm

    StatexDN       <= StatexDP;
    FinBlockxSN    <= FinBlockxSP;
    TENcntxDN      <= (others => '0');
    CntxDO         <= TENcntxDP;
    SavexSO        <= '0';
    NewMsgxSO      <= '0';
    NewBlockSO     <= '0';
    PenUltCyclexSO <= '0';
    OutWrEnxSO     <= '0';

    case StatexDP is
      -------------------------------------------------------------------------
      when idle =>

        if InWrEnxSI = '1' then
          FinBlockxSN <= FinBlockxSI;
	  NewMsgxSO   <= '1';
          NewBlockSO  <= '1';
          TENcntxDN   <= to_unsigned(1, 8);
          StatexDN    <= round;
        end if;

        -------------------------------------------------------------------------
      when round =>
        
        if TENcntxDP = NROUND - 1 then
	  PenUltCyclexSO <= '1';
          if FinBlockxSP = '1' then
	    StatexDN       <= output;
          else
            StatexDN       <= ready;
          end if;
        else
          TENcntxDN <= TENcntxDP+1;
          StatexDN  <= round;
        end if;

        -------------------------------------------------------------------------
      when ready =>
        
        if InWrEnxSI = '1' then
          TENcntxDN   <= to_unsigned(1, 8);
          StatexDN    <= round;
          NewBlockSO  <= '1';
          FinBlockxSN <= FinBlockxSI;
        else
          SavexSO  <= '1';
          StatexDN <= ready;
        end if;
        -------------------------------------------------------------------------
      when output =>
        OutWrEnxSO <= '1';
        StatexDN    <= idle;
        if InWrEnxSI = '1' then
          FinBlockxSN <= FinBlockxSI;
	  NewMsgxSO  <= '1';
          NewBlockSO <= '1';
          TENcntxDN  <= to_unsigned(1, 8);
          StatexDN   <= round;
        end if;
        -------------------------------------------------------------------------
      when others => StatexDN <= idle;
                     
    end case;
    
  end process p_fsm;

  p_mem : process (ClkxCI, RstxRBI)
  begin  -- process p_mem
    if RstxRBI = '0' then               -- asynchronous reset (active low)
      StatexDP    <= idle;
      TENcntxDP   <= (others => '0');
      FinBlockxSP <= '0';
   
    elsif ClkxCI'event and ClkxCI = '1' then  -- rising clock edge
      StatexDP    <= StatexDN;
      TENcntxDP   <= TENcntxDN;
      FinBlockxSP <= FinBlockxSN;

    end if;
  end process p_mem;

end rtl;