------------------------------------------------------------
-- Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Title      : MainLoop
-- Project    : 
-------------------------------------------------------------------------------
-- File       : MainLoop.vhdl
-- Author     : Köppel Benedikt;Schnydrig Mathias  
-- Company    : Integrated Systems Laboratory, ETH Zurich
-- Created    : 2010-10-28
-- Last update: 2011-08-29
-- Platform   : ModelSim (simulation), Synopsys (synthesis)
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: SHA 256 Main Loop
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2010-10-28  1.0      sem10h7 Created
-- 2011-08-29  1.1      kgf     changed the entity name for CSA
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.shapkg.all;

entity MainLoop is
  
  port (
    KKKxDI  : in  std_logic_vector(31 downto 0);
    WKKxDI  : in  std_logic_vector(31 downto 0);
    AtoHxDI : in  h_arr;
    AtoHxDO : out h_arr
    );

end MainLoop;

architecture behave of MainLoop is

  signal S0xD     : std_logic_vector(31 downto 0);
  signal MajxD    : std_logic_vector(31 downto 0);
  signal CHxD     : std_logic_vector(31 downto 0);
  signal S1xD     : std_logic_vector(31 downto 0);
  signal T1sum2xD : std_logic_vector(31 downto 0);
  signal T2xD     : std_logic_vector(31 downto 0);
  signal T1sum1xD : std_logic_vector(31 downto 0);
  signal T1sum3xD : std_logic_vector(31 downto 0);
  signal T1xD     : std_logic_vector(31 downto 0);

  -- carry save adders
--  signal SCAxD  : std_logic_vector(31 downto 0);
--  signal PSAxD  : std_logic_vector(31 downto 0);
--  signal SumAxD : std_logic_vector(32 downto 0);
--  signal SCExD  : std_logic_vector(31 downto 0);
--  signal PSExD  : std_logic_vector(31 downto 0);
--  signal SumExD : std_logic_vector(32 downto 0);

  constant WIDTH : integer := 32;       -- CSA width
  
  component ethz_csa
    generic (
      WIDTH : integer);
    port (
      XxDI : in  std_logic_vector(WIDTH-1 downto 0);
      YxDI : in  std_logic_vector(WIDTH-1 downto 0);
      ZxDI : in  std_logic_vector(WIDTH-1 downto 0);
      CxDO : out std_logic_vector(WIDTH-1 downto 0);
      SxDO : out std_logic_vector(WIDTH-1 downto 0));
  end component;
  

    -- temp signals
  signal CSAC1xD : std_logic_vector(WIDTH-1 downto 0);
  signal CSAS1xD : std_logic_vector(WIDTH-1 downto 0);
  signal CSAC2xD : std_logic_vector(WIDTH-1 downto 0);
  signal CSAS2xD : std_logic_vector(WIDTH-1 downto 0);
  signal CSAC3xD : std_logic_vector(WIDTH-1 downto 0);
  signal CSAS3xD : std_logic_vector(WIDTH-1 downto 0);
  signal CSAC4xD : std_logic_vector(WIDTH-1 downto 0);
  signal CSAS4xD : std_logic_vector(WIDTH-1 downto 0);
  signal CSAC5xD : std_logic_vector(WIDTH-1 downto 0);
  signal CSAS5xD : std_logic_vector(WIDTH-1 downto 0);
  signal CSAC6xD : std_logic_vector(WIDTH-1 downto 0);
  signal CSAS6xD : std_logic_vector(WIDTH-1 downto 0);

  
  
--  component Add32Mod
--    port (
--      a : in  std_logic_vector(31 downto 0);
--      b : in  std_logic_vector(31 downto 0);
--      s : out std_logic_vector(31 downto 0));
--  end component;

begin





  CSA_1: ethz_csa
    generic map (
      WIDTH => WIDTH)
    port map (
      XxDI => KKKxDI,
      YxDI => WKKxDI,
      ZxDI => AtoHxDI(7),
      CxDO => CSAC1xD,
      SxDO => CSAS1xD);
  CSA_2: ethz_csa
    generic map (
      WIDTH => WIDTH)
    port map (
      XxDI => CSAC1xD,
      YxDI => CSAS1xD,
      ZxDI => S1xD,
      CxDO => CSAC2xD,
      SxDO => CSAS2xD);
  CSA_3: ethz_csa
    generic map (
      WIDTH => WIDTH)
    port map (
      XxDI => CSAC2xD,
      YxDI => CSAS2xD,
      ZxDI => CHxD,
      CxDO => CSAC3xD,
      SxDO => CSAS3xD);
  -- CSA.3 is now KKK + WKK + H + S1 + CH

  CSA_4: ethz_csa
    generic map (
      WIDTH => WIDTH)
    port map (
      XxDI => CSAC3xD,
      YxDI => CSAS3xD,
      ZxDI => AtoHxDI(3),
      CxDO => CSAC4xD,
      SxDO => CSAS4xD);
  -- CSA.4 is now CSA.3 + D
  AtoHxDO(4) <= CSAC4xD + CSAS4xD;

  CSA_5: ethz_csa
    generic map (
      WIDTH => WIDTH)
    port map (
      XxDI => CSAC3xD,
      YxDI => CSAS3xD,
      ZxDI => S0xD,
      CxDO => CSAC5xD,
      SxDO => CSAS5xD);

  CSA_6: ethz_csa
    generic map (
      WIDTH => WIDTH)
    port map (
      XxDI => CSAC5xD,
      YxDI => CSAS5xD,
      ZxDI => MajxD,
      CxDO => CSAC6xD,
      SxDO => CSAS6xD);
  
  AtoHxDO(0) <= CSAC6xD + CSAS6xD;
  

  



  
  S0xD  <= (AtoHxDI(0)(1 downto 0)&AtoHxDI(0)(31 downto 2)) xor (AtoHxDI(0)(12 downto 0)&AtoHxDI(0)(31 downto 13)) xor (AtoHxDI(0)(21 downto 0)&AtoHxDI(0)(31 downto 22));
  MajxD <= (AtoHxDI(0) and AtoHxDI(1)) xor (AtoHxDI(0) and AtoHxDI(2)) xor (AtoHxDI(1) and AtoHxDI(2));
  CHxD  <= (AtoHxDI(4) and AtoHxDI(5)) xor ((not AtoHxDI(4)) and AtoHxDI(6));

  S1xD <= (AtoHxDI(4)(5 downto 0)&AtoHxDI(4)(31 downto 6)) xor (AtoHxDI(4)(10 downto 0)&AtoHxDI(4)(31 downto 11)) xor (AtoHxDI(4)(24 downto 0)&AtoHxDI(4)(31 downto 25));






  -- the easy ones
  AtoHxDO(1) <= AtoHxDI(0);
  AtoHxDO(2) <= AtoHxDI(1);
  AtoHxDO(3) <= AtoHxDI(2);
  AtoHxDO(5) <= AtoHxDI(4);
  AtoHxDO(6) <= AtoHxDI(5);
  AtoHxDO(7) <= AtoHxDI(6);

end behave;