------------------------------------------------------------ -- Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich -- http://www.iis.ee.ethz.ch/~sha3 ------------------------------------------------------------ use std.textio.all; library ieee; use ieee.std_logic_textio.all; -- read and write overloaded for std_logic use ieee.std_logic_1164.all; use work.simulstuff.all; use work.SHA256MainTbPkg.all; use work.sha_pack.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------- entity SHA256MainTb is -- a testbench does not connect to any higher level of hierarchy end SHA256MainTb; ------------------------------------------------------------------------------- architecture behavioral of SHA256MainTb is component SHA256Main port ( MessageInxDI : in expmess_arr; HInxDI : in h_arr; CLKxCI : in std_logic; RSTxRBI : in std_logic; VALIDOUTxSO : out std_logic; HOutxDO : out h_arr; MessageReadyxSI : in std_logic; MessageReceivedxSO : out std_logic); end component; file exprespfile : text open read_mode is EXPRESP_FILENAME; signal MessageInxD : expmess_arr; signal HInxD : h_arr; -- input values of H signal RSTxRB : std_logic; signal VALIDOUTxS : std_logic; signal HOutxD : h_arr; signal MessageReadyxS : std_logic; signal MessageReceivedxS : std_logic; ------------------------------------------------------------------------------- -- BEGIN ------------------------------------------------------------------------------- begin SHA256Main_1 : SHA256Main port map ( MessageInxDI => MessageInxD, HInxDI => HInxD, CLKxCI => CLKxC, RSTxRBI => RSTxRB, VALIDOUTxSO => VALIDOUTxS, HOutxDO => HOutxD, MessageReadyxSI => MessageReadyxS, MessageReceivedxSO => MessageReceivedxS); -- ExpResPickup : process -- variable ResponsexD : responseRecordType; -- begin -- PickupLoop : loop -- wait until (CLKxC'event and CLKxC = '1') or EndOfSimxS = true; -- -- leave the loop if there are no more stimuli left -- exit PickupLoop when EndOfSimxS = true; -- if VALIDOUTxS = '1' then -- -- update expected response from file -- ResponsexD := GetExpectedResponseRecord(exprespfile); -- ExpResponseRecxD.HxD ResponsexD.HxD; -- end if; -- end loop PickupLoop; -- file_close(exprespfile); -- close the file -- wait; -- end process ExpResPickup; ClkGen : ClockGenerator( ClkxC => CLKxC, CLKPHASELOW => CLK_PHASE_LOW, CLKPHASEHIGH => CLK_PHASE_HIGH); -- obtain stimuli and apply it to MUT ---------------------------------------------------------------------------- StimAppli : process begin AppliLoop : while not (endfile(stimulifile)) loop wait until CLKxC'event and CLKxC = '1'; -- apply stimulus to MUT StimuliRecxD <= GetStimuliRecord(stimulifile); -- wait until time has come for stimulus application wait for STIMULI_APPLICATION_TIME; MessageInxD <= StimuliRecxD.MessageInxD; HInxD <= StimuliRecxD.HInxD; RSTxRB <= StimuliRecxD.RSTxRB; MessageReadyxS <= StimuliRecxD.MessageReadyxS; end loop AppliLoop; -- tell clock generator to stop at the end of current cycle -- because stimuli have been exhausted EndOfSimxS <= true; -- close the file file_close(stimulifile); wait; end process StimAppli; -- acquire actual response from MUT and have it checked ---------------------------------------------------------------------------- RespAcqui : process -- variables for accounting of mismatching responses variable respmatch : respMatchArray; variable respaccount : respaccounttype := (0, 0, 0, 0, 0, 0); -- variable for counting the lines written to the simulation report variable simRepLineCount : natural := 0; variable ResponsexD : responseRecordType; begin -- This wait statement is only useful if the stimuli file is empty. In that case -- EndOfSimxS gets true after one delta delay. Without that wait statement -- the following exit statement would be executed before EndOfSimxS gets true. wait until CLKxC'event and CLKxC = '0'; ResponsexD := GetExpectedResponseRecord(exprespfile); ExpResponseRecxD.HOutxD <= ResponsexD.HOutxD; AcquiLoop : loop -- leave the loop if there are no more stimuli left exit AcquiLoop when EndOfSimxS = true; wait until CLKxC'event and CLKxC = '1'; -- wait until time has come for response acquisition wait for RESPONSE_ACQUISITION_TIME; ActResponseRecxD.HOutxD <= HOutxD; if VALIDOUTxS = '1' then ResponsexD := GetExpectedResponseRecord(exprespfile); ExpResponseRecxD.HOutxD <= ResponsexD.HOutxD; -- compare the actual with the expected responses CheckResponse(ActResponseRecxD, ExpResponseRecxD, respmatch, respaccount); -- add a trace line to report file PutSimulationReportTrace(simreptfile, StimuliRecxD, ActResponseRecxD, respmatch, respaccount, simRepLineCount); -- add extra failure message to report file if necessary PutSimulationReportFailure(simreptfile, ExpResponseRecxD, respmatch); end if; end loop AcquiLoop; -- when the present clock cycle is the final one of this run -- then establish a simulation report summary and write it to file PutSimulationReportSummary(simreptfile, respaccount); -- close the file file_close(simreptfile); file_close(exprespfile); report "Simulation run completed!"; wait; end process RespAcqui; end architecture behavioral;