------------------------------------------------------------
-- Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Title      : Carry Save Adder
-- Project    : 
-------------------------------------------------------------------------------
-- File       : ethz_csa.vhdl
-- Author     : Köppel Benedikt;Schnydrig Mathias  
-- Company    : Integrated Systems Laboratory, ETH Zurich
-- Created    : 2010-12-16
-- Last update: 2011-08-29
-- Platform   : ModelSim (simulation), Synopsys (synthesis)
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: Carry Save Adder
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2010-12-16  1.0      sem10h7	Created
-- 2011-08-29  1.1      kgf     renamed the instance to avoid name conflicts
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;



-------------------------------------------------------------------------------
-- This is only a Modulo-WIDTH CSA!
-- because we're only interested in Addition-Modulo, we can omit everything
-------------------------------------------------------------------------------




entity ethz_csa is
  
  generic (
    WIDTH : integer := 32);

  port (
    XxDI : in std_logic_vector(WIDTH-1 downto 0);
    YxDI : in std_logic_vector(WIDTH-1 downto 0);
    ZxDI : in std_logic_vector(WIDTH-1 downto 0);

    CxDO : out std_logic_vector(WIDTH-1 downto 0);
    SxDO : out std_logic_vector(WIDTH-1 downto 0)
    );

end ethz_csa;

architecture behave of ethz_csa is
  signal CFULLxDO : std_logic_vector(WIDTH downto 0);

begin  -- behave

  SxDO <= XxDI xor YxDI xor ZxDI;
  
  CFULLxDO <= ( (XxDI and YxDI) or (XxDI and ZxDI) or (YxDI and ZxDI) ) & '0';
  CxDO <= CFULLxDO(WIDTH-1 downto 0);

end behave;