------------------------------------------------------------ -- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich -- http://www.iis.ee.ethz.ch/~sha3 ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity gf4inv is port ( AxDI : in std_logic_vector(3 downto 0); AInvxDO : out std_logic_vector(3 downto 0)); end gf4inv; architecture rtl of gf4inv is signal AAxD : std_logic; begin -- rtl AAxD <= AxDI(1) xor AxDI(2) xor AxDI(3) xor (AxDI(1) and AxDI(2) and AxDI(3)); -- aA AInvxDO(0) <= AAxD xor AxDI(0) xor (AxDI(0) and AxDI(2)) xor (AxDI(1) and AxDI(2)) xor (AxDI(0) and AxDI(1) and AxDI(2)); AInvxDO(1) <= (AxDI(0) and AxDI(1)) xor (AxDI(0) and AxDI(2)) xor (AxDI(1) and AxDI(2)) xor AxDI(3) xor (AxDI(1) and AxDI(3)) xor (AxDI(0) and AxDI(1) and AxDI(3)); AInvxDO(2) <= (AxDI(0) and AxDI(1)) xor AxDI(2) xor (AxDI(0) and AxDI(2)) xor AxDI(3) xor (AxDI(0) and AxDI(3)) xor (AxDI(0) and AxDI(2) and AxDI(3)); AInvxDO(3) <= AAxD xor (AxDI(0) and AxDI(3)) xor (AxDI(1) and AxDI(3)) xor (AxDI(2) and AxDI(3)); end rtl;