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-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity gf4sqr is
  port (
    AxDI  : in  std_logic_vector(3 downto 0);
    A2xDO : out std_logic_vector(3 downto 0));
    
end gf4sqr;

architecture rtl of gf4sqr is

begin  -- rtl

  A2xDO(0) <= AxDI(0) xor AxDI(2);
  A2xDO(1) <= AxDI(2);
  A2xDO(2) <= AxDI(1) xor AxDI(3);
  A2xDO(3) <= AxDI(3);
  
end rtl;