------------------------------------------------------------
-- Copyright: 2011 George Mason University, Virginia USA
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
-- =====================================================================

-- Copyright © 2010-2011 by Cryptographic Engineering Research Group (CERG),

-- ECE Department, George Mason University

-- Fairfax, VA, U.S.A.

-- =====================================================================


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

use work.sha3_blake_package.ALL;
use work.sha3_pkg.all;

entity gmu_blake_datapath is	 	
	generic (	  	   
		b : integer := 512;
		iw : integer := 32;
		h : integer := 256;
		ADDER_TYPE : integer := SCCA_BASED);
	port (
		-- external

		clk : in std_logic;
		rst : in std_logic;
		
		din  : in std_logic_vector(b-1 downto 0);	
		t	 : in std_logic_vector(iw*2-1 downto 0);
		dout : out std_logic_vector(h-1 downto 0);	
	
		--fsm 2			  		

		round : in std_logic_vector(4 downto 0);	
		em : in std_logic;
		lm : in std_logic;
		eh : in std_logic;											
		er : in std_logic;		
		sf : in std_logic
	);				  
end gmu_blake_datapath;

architecture struct of gmu_blake_datapath is   
	constant mw 			: integer := b;		 
	constant log2b			: integer := log2( b );
	constant log2bzeros		: std_logic_vector(log2b-1 downto 0) := (others => '0');	
	constant bzeros			: std_logic_vector(b-1 downto 0) := (others => '0');
	constant bhalfzeros		: std_logic_vector(b/2-1 downto 0) := (others => '0');
	-------------


	constant iv : std_logic_vector(b/2-1 downto 0) := get_iv( h, iw );
	signal hinit,rdprime, rmux : std_logic_vector(b/2 - 1 downto 0);
	signal rinit, rin, r, rprime : std_logic_vector(b-1 downto 0);	
	signal m : std_logic_vector(b-1 downto 0);
		
	constant cons : std_logic_vector(b-1 downto 0) := get_cons( h, b, iw );
1 downto 0);  			  -- 8 = b size, 4 = b/2 size


	type std_logic_matrix is array (natural range <>) of std_logic_vector(iw - 1 downto 0) ;
	function wordmatrix2blk  	(x : std_logic_matrix) return std_logic_vector is
		variable retval : std_logic_vector(b-1 downto 0);
	begin
		for i in 0 to 15 loop
			retval(iw*(i+1) - 1 downto iw*i) := x(15-i);
		end loop;
		return retval;
	end wordmatrix2blk;
	function blk2wordmatrix  	(x : std_logic_vector; blksize : integer ) return std_logic_matrix is
		variable retval : std_logic_matrix(0 to blksize-1);
	begin
		for i in 0 to blksize-1 loop
			retval(blksize-1-i) := x(iw*(i+1) - 1 downto iw*i);
		end loop;
		return retval;
	end blk2wordmatrix;	
		
	signal v1, v2, v2_perm, v2_revert, v3 : std_logic_matrix( 0 to 15 ); 
	signal cp : std_logic_matrix(0 to 7);	 
	
	type bot_permute_type is array ( 0 to 15 ) of integer;
	constant bot_permute : bot_permute_type := ( 0,1,2,3,5,6,7,4,10,11,8,9,15,12,13,14 );
	
	signal treg : std_logic_vector(iw*2-1 downto 0);
	-- debug			  

	signal rinit_m, r_m, r_v21, r_v22, r_r : std_logic_matrix(0 to 15);	
begin		
	-- debug

	rinit_m <= blk2wordmatrix( rin, 16 );		 
	r_m <= blk2wordmatrix( m, 16 );	
	r_v21 <= blk2wordmatrix( wordmatrix2blk(v2_perm), 16 );	
	r_v22 <= blk2wordmatrix( wordmatrix2blk(v2_revert), 16 );	
	r_r <= blk2wordmatrix( r, 16 );	
	
	mregInst : regna generic map (n => b, INIT => bzeros) port map (clk => clk, rst => rst, en => lm, input => din, output => m );	
	tregInst : regna generic map (n => 2*iw, INIT => bzeros(2*iw-1 downto 0)) port map (clk => clk, rst => rst, en => lm, input => t, output => treg );

	rmux <= iv when sf = '1' else rdprime;
	rinit <= rmux &  cons(b-1 downto b-iw*4)  & 
			(treg(iw-1 downto 0) xor cons(b-1-iw*4 downto b-iw*5)) &  (treg(iw-1 downto 0) xor cons(b-iw*5-1 downto b-iw*6)) &
			(treg(2*iw-1 downto iw) xor cons(b-1-iw*6 downto b-iw*7))  & (treg(2*iw-1 downto iw) xor cons(b-iw*7-1 downto b-iw*8));		
	hreg_gen : regna generic map ( N => b/2, init => bhalfzeros ) port map (clk => clk, rst => rst, en => eh, input => rmux, output => hinit );	
	
	rin <= rinit when (eh = '1') else rprime;
	r_gen : regna generic map ( N => b, init => bzeros ) port map (clk => clk, rst => rst, en => er, input => rin, output => r );		
		
	v1 <= blk2wordmatrix(r, 16);
	perm4_gen : entity work.permute4xor(muxbased) 
		generic map (h => h, b => b, iw => iw) 
		port map ( clk => clk, em => eh, m => m, round => round, consout => consout );
	
	consregInst : regna generic map (n => b/2, INIT => bzeros(b/2-1 downto 0)) port map (clk => clk, rst => rst, en => '1', input => consout, output => consreg ); 
	cp <= blk2wordmatrix(consreg, 8);
	glvl1 : for i in 0 to 3 generate
		g0123 : entity work.gfunc_modified(struct) 	generic map ( iw => iw, h => h, ADDER_TYPE => ADDER_TYPE )
			port map ( 	ain => v1(i), bin => v1(i+4), cin => v1(i+8), din => v1(i+12), -- state in

				  		const_0 => cp(2*i), const_1 => cp(2*i + 1), -- constant in

					 	aout =>  v2(i), bout => v2(i+4), cout=> v2(i+8),dout => v2(i+12)); -- state out

	end generate;
	
	v2_gen : for i in 0 to 15 generate
		v2_perm( bot_permute(i) ) <= v2( i ); 
		v2_revert( i ) <= v2( bot_permute(i) );
	end generate;
	
	--v3 when round(0) = '1' else v2_revert;		

	v3 <= v2_perm when round(0) = '0' else v2_revert;		
	rprime <= wordmatrix2blk(v3);			
	--finalization				

	rdprime <= hinit xor r(b-1 downto b/2) xor r(b/2-1 downto 0);
	dout <= rdprime;
end struct;