------------------------------------------------------------ -- Copyright: 2011 George Mason University, Virginia USA -- http://www.iis.ee.ethz.ch/~sha3 ------------------------------------------------------------ -- ===================================================================== -- Copyright © 2010-2011 by Cryptographic Engineering Research Group (CERG), -- ECE Department, George Mason University -- Fairfax, VA, U.S.A. -- ===================================================================== -- Possible generic(s) values: -- adder_type = {SCCA_BASED, CSA_BASED} -- -- adder_type describes the type of adders being used in the critical paths. They are : -- SCCA_BASED => Standard Carry Chain Addition in FPGA. This is a simple '+' sign. -- CSA_BASED => Carry Save Adder. library ieee; use ieee.std_logic_1164.all; use work.sha3_pkg.all; use work.sha3_blake_package.all; entity gmu_blake_top is generic ( adder_type : integer := SCCA_BASED ); port ( ClkxCI : in std_logic; -- Rising Edge Triggered Clock RstxRBI : in std_logic; -- Active-low, asynchronous Reset Signal ScanInxTI : in std_logic; ScanOutxTO : out std_logic; ScanEnxTI : in std_logic; InEnxSI : in std_logic; -- Input Enable FinBlockxSI : in std_logic; -- Final Block DataxDI : in std_logic_vector(511 downto 0); -- Input Data MsgLenxDI : in std_logic_vector(63 downto 0); OutEnxSO : out std_logic; -- Output Enable PenUltCyclexSO : out std_logic; -- Penultimate Cycle DataxDO : out std_logic_vector(255 downto 0) -- Output Data ); end gmu_blake_top; architecture structure of gmu_blake_top is constant h : integer := 256; constant b : integer := get_b( h ); constant iw : integer := get_iw( h ); constant version : integer := SHA3_ROUND3; signal er, em, eh, sf, lm : std_logic; signal round : std_logic_vector(4 downto 0); begin control_gen : entity work.gmu_blake_control(beh) port map ( clk => ClkxCI, rst => RstxRBI, InWrEnxSI => InEnxSI, FinBlockxSI => FinBlockxSI, OutWrEnxSO => OutEnxSO, PenUltCyclexSO => PenUltCyclexSO, round => round, er => er, em => em, eh => eh, sf => sf, lm => lm ); datapath_gen : entity work.gmu_blake_datapath(struct) generic map ( b => b, iw => iw, h => h, ADDER_TYPE => adder_type ) port map ( clk => ClkxCI, rst => RstxRBI, din => DataxDI, dout => DataxDO, t => MsgLenxDI, round => round, er => er, em => em, eh => eh, sf => sf, lm => lm ); end structure;