------------------------------------------------------------
-- Copyright: 2011 George Mason University, Virginia USA
--            http://www.iis.ee.ethz.ch/~sha3
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-- =====================================================================

-- Copyright © 2010-2011 by Cryptographic Engineering Research Group (CERG),

-- ECE Department, George Mason University

-- Fairfax, VA, U.S.A.

-- =====================================================================


library ieee;
use ieee.std_logic_1164.all; 

-- n-bits asynchonous register 


entity regna is
	generic (  
		RST_ACTIVE_VALUE : std_logic := '0';
		N : integer := 32;
		INIT : std_logic_vector
	);
	port ( 	  
	    clk 	: in std_logic;
		rst 	: in std_logic;
	    en 		: in std_logic; 
		input  	: in std_logic_vector(N-1 downto 0);
        output 	: out std_logic_vector(N-1 downto 0)
	);
end regna;

architecture struct of regna is

begin	
	gen : process( rst, clk )
	begin		
		if ( rst = RST_ACTIVE_VALUE ) then
			output <= INIT;
		elsif rising_edge( clk ) then
			if ( en = '1' ) then
				output <= input;
			end if;
		end if;
	end process;
end struct;