------------------------------------------------------------
-- Copyright: 2011 George Mason University, Virginia USA
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
-- =====================================================================

-- Copyright © 2010-2011 by Cryptographic Engineering Research Group (CERG),

-- ECE Department, George Mason University

-- Fairfax, VA, U.S.A.

-- =====================================================================


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.sha3_pkg.all;
						  
entity counterna is
	generic ( 	   
		RST_ACTIVE_VALUE : std_logic := '0';
		N 	: integer := 2	
	);
	port ( 	  
		clk : in std_logic;
		rst : in std_logic;
	    load : in std_logic;
	    en : in std_logic; 
        output : out std_logic_vector(N-1 downto 0)
	);
end counterna;

architecture struct of counterna is
   	signal temp : std_logic_vector(N-1 downto 0);
begin			
	gen : process( rst, clk )
	begin		
		if rst = RST_ACTIVE_VALUE then
			temp <= (others => '0');
		elsif rising_edge( clk ) then
			if (load = '1' ) then
				temp <= (others => '0');
			elsif ( en = '1' ) then
				temp <= temp + 1;
			end if;
		end if;				
	end process;  	
	output <= temp;
end struct;