------------------------------------------------------------ -- Copyright: 2011 George Mason University, Virginia USA -- http://www.iis.ee.ethz.ch/~sha3 ------------------------------------------------------------ -- ===================================================================== -- Copyright © 2010-2011 by Cryptographic Engineering Research Group (CERG), -- ECE Department, George Mason University -- Fairfax, VA, U.S.A. -- ===================================================================== library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; use work.sha3_pkg.all; use work.groestl_pkg.all; -- Groestl datapath for quasi-pipelined architecture -- rom_style = {DISTRIBUTED, COMBINATIONAL} --- all combinations are allowed entity gmu_groestl_datapath is generic (n :integer := GROESTL_DATA_SIZE_SMALL; hs : integer := HASH_SIZE_256; rom_style : integer := DISTRIBUTED); port( clk : in std_logic; rst : in std_logic; -- processing init1 : in std_logic; init2 : in std_logic; init3 : in std_logic; last_cycle : in std_logic; finalization : in std_logic; wr_state : in std_logic; wr_result : in std_logic; load_ctr : in std_logic; wr_ctr : in std_logic; p_mode : in std_logic; din : in std_logic_vector(511 downto 0); dout : out std_logic_vector(255 downto 0)); end gmu_groestl_datapath; architecture folded_x2 of gmu_groestl_datapath is constant log2mw : integer := log2( n ); constant log2mwzeroes : std_logic_vector(log2mw-1 downto 0) := (others => '0'); constant zero : std_logic_vector(n-1 downto 0):= (others=>'0'); signal from_final, to_round, from_register, to_final : std_logic_vector(n-1 downto 0); signal init_value, to_register, to_reg, inter_value : std_logic_vector(n-1 downto 0); signal ctr : std_logic_vector(3 downto 0); signal round : std_logic_vector(7 downto 0); -- signal to_round1, to_round2, m1, m2 : std_logic_vector(n/2-1 downto 0); begin -- to_round1 downto n/2); -- to_round2 downto 0); -- m1 downto n/2); -- m2 downto 0); init_value <= din when init1='1' else din xor from_final; inter_value <= init_value when init2='1' else from_register; to_round <= (from_register xor from_final) when finalization='1' else inter_value; to_reg <= to_final when last_cycle='1' else to_register; -- storage register for intermediate values state_reg : regna generic map(N=>n, init=>zero(n-1 downto 0)) port map (clk => clk, rst => rst, en => wr_state, input => to_reg, output => from_register ); -- round counter rd_num : counterna generic map (N =>4) port map (clk=>clk, rst=>rst, load=>load_ctr, en=>wr_ctr, output=>ctr); round <= zero(3 downto 0) & ctr; -- quasi-pipelining round rounds : entity work.groestl_pq(round3_pipelined) generic map (n=>n, rom_style=>rom_style) port map (clk=>clk, rst=>rst, p_mode=>p_mode, round=>round, input=>to_round, output=>to_register); -- initialization vectors for different versions of Groestl to_final <= GROESTL_INIT_VALUE_256 when init3='1' else to_register xor from_final; -- final message digest storage register final_reg : regna generic map(N=>n, init=>zero(n-1 downto 0)) port map (clk => clk, rst => rst, en => wr_result, input => to_final, output => from_final ); -- parallel input serial output dout <= from_final(hs-1 downto 0); end folded_x2;