------------------------------------------------------------
-- Copyright: 2011 George Mason University, Virginia USA
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
-- =====================================================================

-- Copyright © 2010-2011 by Cryptographic Engineering Research Group (CERG),

-- ECE Department, George Mason University

-- Fairfax, VA, U.S.A.

-- =====================================================================


-- Possible generic values: 

-- 		rom_style = {DISTRIBUTED, COMBINATIONAL}	


library ieee;
use ieee.std_logic_1164.all;
use work.sha3_pkg.all;
use work.groestl_pkg.all;	 
		

entity gmu_groestl_top is
        generic (
                rom_style : integer := DISTRIBUTED); 
        port (
                ClkxCI      : in  std_logic;  -- Rising Edge Triggered Clock

                RstxRBI     : in  std_logic;  -- Active-low, asynchronous Reset Signal

                ScanInxTI   : in  std_logic;
                ScanOutxTO  : out std_logic;
                ScanEnxTI   : in  std_logic;
                InEnxSI     : in  std_logic;  -- Input Enable

                FinBlockxSI : in  std_logic;  -- Final Block

                DataxDI     : in  std_logic_vector(511 downto 0);  -- Input Data                          


                OutEnxSO       : out std_logic;  -- Output Enable

                PenUltCyclexSO : out std_logic;  -- Penultimate Cycle

                DataxDO        : out std_logic_vector(255 downto 0)  -- Output Data

        );	     
end gmu_groestl_top;


architecture structure of gmu_groestl_top is  	
	constant GROESTL_DATA_SIZE : integer := GROESTL_DATA_SIZE_SMALL;
	constant version : integer := SHA3_ROUND3;
	signal init1, init2, init3, finalization, wr_state, wr_result	:std_logic;
	signal load_ctr, wr_ctr, p_mode, last_cycle	:std_logic;
begin

dp_fx2_256 : entity work.gmu_groestl_datapath(folded_x2) 
		generic map(n=>GROESTL_DATA_SIZE, hs=> HASH_SIZE_256, rom_style=>rom_style)
		port map (clk=>ClkxCI, rst=>RstxRBI,  
		init1=>init1, init2=>init2, init3=>init3, finalization=>finalization, last_cycle=>last_cycle,
		wr_state=>wr_state, wr_result=>wr_result, load_ctr=>load_ctr, wr_ctr=>wr_ctr, p_mode=>p_mode,
		din=>DataxDI, dout=>DataxDO );	  	
		
ctrl : entity work.gmu_groestl_control(beh) 		
		port map ( clk	=> ClkxCI, rst=>RstxRBI, 
		init1=>init1, init2=>init2, init3=>init3, finalization=>finalization, last_cycle=>last_cycle,
		wr_state=>wr_state, wr_result=>wr_result, load_ctr=>load_ctr, wr_ctr=>wr_ctr, p_mode=>p_mode,
		InWrEnxSI => InEnxSI, FinBlockxSI => FinBlockxSI, OutWrEnxSO => OutEnxSO, PenUltCyclexSO => PenUltCyclexSO);		
end structure;