------------------------------------------------------------
-- Copyright: 2011 George Mason University, Virginia USA
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
-- =====================================================================

-- Copyright © 2010-2011 by Cryptographic Engineering Research Group (CERG),

-- ECE Department, George Mason University

-- Fairfax, VA, U.S.A.

-- =====================================================================

			 
-- set-reset asynchronous register


library ieee;
use ieee.std_logic_1164.all;

entity sr_rega is
	generic (	 
		RST_ACTIVE_VALUE : std_logic := '0';
	  	INIT : std_logic := '0'
	);
	port (					
		rst			: in std_logic;
		clk 		: in std_logic;
		set     	: in std_logic;
		clr         : in std_logic;
		output		: out std_logic
	);				 
end sr_rega;

architecture struct of sr_rega is   
	signal outputWire : std_logic;
begin	   					  	   	
	reg_gen : process( rst, clk )
	begin	
		if ( rst = RST_ACTIVE_VALUE ) then
			outputWire <= INIT;
		elsif rising_edge(clk) then  
			outputWire <= set or ((not clr) and outputWire);			
		end if;	
	end process;
	output <= outputWire;
end struct;