------------------------------------------------------------
-- Copyright: 2011 George Mason University, Virginia USA
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
-- =====================================================================

-- Copyright © 2010-2011 by Cryptographic Engineering Research Group (CERG),

-- ECE Department, George Mason University

-- Fairfax, VA, U.S.A.

-- =====================================================================

	 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; 
use work.sha3_pkg.all;
use work.sha3_jh_package.all;

entity gmu_jh_control is		
	generic (
		RST_ACTIVE_VALUE : std_logic := '0' );
	port (					
		rst			: in std_logic;
		clk			: in std_logic;
		
		-- processing

		srdp 	: out std_logic;
		er		: out std_logic;
		sf		: out std_logic; 
		erf 	: out std_logic;  -- 

		
		InEnxSI		: in std_logic;
		FinBlockxSI	: in std_logic;
		
		OutEnxSO	: out std_logic;
		PenUltCyclexSO : out std_logic		
	);	 			 
end gmu_jh_control;

architecture beh of gmu_jh_control is				   	 
	type stateType is ( initState, idleState, hashBlockState, finBlockState );
	signal cstate, nstate : stateType;
	
	signal lastBlockFlag, lastBlockSet, lastBlockClr : std_logic;	
	signal roundCtr : std_logic_vector(5 downto 0);
	signal loadRoundCtr, incRoundCtr : std_logic;	
	signal roundDoneComp : std_logic;	 
	
	signal sfSet, sfClr, sfFlag : std_logic;
	constant roundNumber : integer := 42;
begin											   
	roundCtrGen:
		process( rst, clk )
		begin
			if (rst = RST_ACTIVE_VALUE) then
				roundCtr <= (others => '0');
			elsif rising_edge( clk ) then
				if loadRoundCtr = '1' then
					roundCtr <= (others => '0');					
				elsif incRoundCtr = '1' then
					roundCtr <= roundCtr + 1;
				end if;
			end if;
		end process;
	incRoundCtr <= '1' when (cstate = hashBlockState ) else '0';
	loadRoundCtr <= '1' when (cstate = idleState or cstate = finBlockState) else '0';	
	roundDoneComp <= '1' when roundCtr = roundNumber-1 else '0';	  

	stateReg:
		process( rst, clk )
		begin
			if (rst = RST_ACTIVE_VALUE) then
				cstate <= initState;
			elsif rising_edge( clk ) then
				cstate <= nstate;
			end if;
		end process;
	
	nextStateComb:
		process( cstate, InEnxSI, roundDoneComp, lastBlockFlag )
		begin																				
			case cstate is
				when initState =>
					nstate <= idleState;
				when idleState =>
					if InEnxSI = '1' then
						nstate <= hashBlockState;
					else
						nstate <= idleState;
					end if;			
				when hashBlockState =>
					if roundDoneComp = '1' then	
						nstate <= finBlockState;
					else
						nstate <= hashBlockState;
					end if;				
				when finBlockState =>
					if lastBlockFlag = '1' then 
						nstate <= idleState;
					elsif InEnxSI = '1' then
						nstate <= hashBlockState;
					else
						nstate <= finBlockState;
					end if;			
			end case;
		end process;
	
	
	
	lastBlockInst: 
		entity work.sr_rega(struct) 
		port map ( rst => rst, clk => clk, set => lastBlockSet, clr => lastBlockClr, output => lastBlockFlag );
	lastBlockSet <= '1' when (cstate = idleState or cstate = finBlockState) and (FinBlockxSI = '1' and InEnXSI = '1') else '0';
	lastBlockClr <= '1' when (cstate = idleState) else '0';
	
	sfInst: 
		entity work.sr_rega(struct) 
		port map ( rst => rst, clk => clk, set => sfSet, clr => sfClr, output => sfFlag );
	sfSet <= '1' when (cstate = initState or (cstate = finBlockState and lastBlockFlag = '1')) else '0';
	sfClr <= '1' when (cstate = idleState and InEnxSI = '1') else '0';
	
	-- Output

	sf <= sfFlag;
	er <= '1' when 	(cstate = idleState) or								 
					(cstate = hashBlockState) or
					(cstate = finBlockState and InEnxSI = '1') else '0';
	srdp <= '1' when (cstate = idleState) or 						
					 (cstate = finBlockState and InEnxSI = '1') else '0';
	erf <= '1' when (cstate = idleState) or
					(cstate = finBlockState and (InEnxSI = '1'or lastBlockFlag = '1')) else '0' ;
	PenUltCyclexSO <= '1' when (cstate = hashBlockState and roundDoneComp = '1' and lastBlockFlag = '0') or
								(cstate = finBlockState and lastBlockFlag = '1') else '0';
	OutEnxSO 	<= '1' when (cstate = finBlockState and lastBlockFlag = '1') else '0';
	
end beh;