------------------------------------------------------------
-- Copyright: 2011 George Mason University, Virginia USA
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
-- =====================================================================

-- Copyright © 2010-2011 by Cryptographic Engineering Research Group (CERG),

-- ECE Department, George Mason University

-- Fairfax, VA, U.S.A.

-- =====================================================================


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

use work.sha3_jh_package.all;
use work.sha3_pkg.all;

entity gmu_jh_datapath_mem is	
	port (
		-- external

		clk : in std_logic;	 
		rst : in std_logic;
		din  : in std_logic_vector(511 downto 0);	
		dout : out std_logic_vector(255 downto 0);	
		
		--fsm 2			  		

		round : in std_logic_vector(5 downto 0);
		er : in std_logic;
		sf : in std_logic;
		srdp : in std_logic
	);				  
end gmu_jh_datapath_mem;


architecture struct of gmu_jh_datapath_mem is 
	--input		  

	signal min_out : std_logic_vector(mw-1 downto 0);
	
	-- round constant

	signal crd_out, crd_out_pre : std_logic_vector(crw-1 downto 0);
	
	-- round		

	signal rd_out : std_logic_vector(b-1 downto 0);
	
	
	signal g, dg : std_logic_vector(b-1 downto 0);
	signal rin, rout : std_logic_vector(b-1 downto 0);
	signal hp, hm : std_logic_vector(b-1 downto 0);
	signal hp_or_iv : std_logic_vector(b-1 downto 0);
	constant iv : std_logic_vector(b-1 downto 0) := get_iv( 256 );
	
	
	-- debug  						   

	-- signal crdo : std_logic_vector(b-1 downto 0);

	-- constant zeros : std_logic_vector(b-1-crw downto 0) := (others => '0');

	-- signal dg_m, rin_m, rout_m, rd_out_m, crd_out_m, hm_m, hp_m : std_logic_matrix;

begin						
	-- input register (for xor at the last round of a block )

	min_reg : regna 
		generic map ( N => mw, init => mwzeros ) 
		port map ( clk => clk, rst => rst, en => srdp, input => din, output => min_out );
		
	-- input to r reg

	hm <= ( din xor hp_or_iv(b-1 downto b/2) ) & hp_or_iv(b/2-1 downto 0);	
	hp_or_iv <= iv when sf = '1' else hp;	
	
	-- group (rearrange them into correct order)		   

	g <= form_group( hm, b, crw );
	rin <= g when srdp = '1' else rd_out;

	--R registers

	rreg_gen : regna 
		generic map ( N => b, init => bzeros ) 
		port map ( clk => clk, rst => rst, en => er, input => rin, output => rout );		
		
	-- output to round function	 

	dg <= degroup( rout, b, crw );
 	hp <= dg(b-1 downto b/2) & ( min_out xor dg(b/2-1 downto 0) );
		
	--- ////////////////////////////////////

	-- round constant (generate using generator)		

	crd_out_pre <= rc_cons( conv_integer(round));	
	uu1: process ( rst, clk ) 
	begin				
		if ( rst = '0' ) then
		   crd_out <= (others => '0');
		elsif rising_edge( clk ) then
			crd_out <= crd_out_pre;
		end if;			
	end process;	 

	
	-- ROUND

	rd_gen 	: entity work.jh_rd(struct) 
		generic map ( bw => b, cw => crw  )
		port map ( input => rout, cr => crd_out, output => rd_out );
	dout <= hp(255 downto 0);
	
	--	--debug

	-- rin_m <= blk2wordmatrix_inv( rin );

	-- rout_m <= blk2wordmatrix_inv( rout );

	-- rd_out_m <= blk2wordmatrix_inv( rd_out );

--	dg_m <= blk2wordmatrix_inv( dg );

--	hp_m <= blk2wordmatrix_inv( hp );

--	hm_m <= blk2wordmatrix_inv( hm );

	-- crdo <= crd_out & zeros;

	-- crd_out_m <= blk2wordmatrix_inv( crdo );

end struct;		   


-- ===============================

-- ============ RC ON THE FLY ===================

-- ===============================


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

use work.sha3_jh_package.all;
use work.sha3_pkg.all;

entity gmu_jh_datapath_otf is	
	port (
		-- external

		clk : in std_logic;
		rst : in std_logic;
		din  : in std_logic_vector(511 downto 0);	
		dout : out std_logic_vector(255 downto 0);	
		
		--fsm 2			  		

		erf : in std_logic;
		er : in std_logic;
		sf : in std_logic;
		srdp : in std_logic		
	);				  
end gmu_jh_datapath_otf;

architecture struct of gmu_jh_datapath_otf is  	
	--input		  

	signal min_out : std_logic_vector(mw-1 downto 0);	
	-- round constant

	signal crd_out : std_logic_vector(crw-1 downto 0);
	signal crdp : std_logic_vector(crw-1 downto 0);
	-- round		

	signal rd_out : std_logic_vector(b-1 downto 0);	
	signal g, dg : std_logic_vector(b-1 downto 0);
	signal rin, rout : std_logic_vector(b-1 downto 0);
	signal hp, hm : std_logic_vector(b-1 downto 0);
	signal hp_or_iv : std_logic_vector(b-1 downto 0);			
	constant iv : std_logic_vector(b-1 downto 0) := get_iv( 256 );

	-- debug  						   

--	signal crdo : std_logic_vector(b-1 downto 0);

--	constant zeros : std_logic_vector(b-1-crw downto 0) := (others => '0');

	signal dg_m, rin_m, rout_m, rd_out_m, crd_out_m, hm_m, hp_m : std_logic_matrix;
begin								
	
	-- input register (for xor at the last round of a block )

	min_reg : regna 
		generic map ( N => mw, init => mwzeros ) 
		port map ( clk => clk, rst => rst, en => srdp, input => din, output => min_out );
	-- input to r reg

	hm <= ( din xor hp_or_iv(b-1 downto b/2) ) & hp_or_iv(b/2-1 downto 0);	
	hp_or_iv <= iv when sf = '1' else hp;	
	
	-- group (rearrange them into correct order)		   

	g <= form_group( hm, b, crw );
	rin <= g when srdp = '1' else rd_out;

	--R registers

	rreg_gen : regna 
		generic map ( N => b, init => bzeros ) 
		port map ( clk => clk, rst => rst, en => er, input => rin, output => rout );		
		
	-- output to round function	 

	dg <= degroup( rout, b, crw );
 	hp <= dg(b-1 downto b/2) & ( min_out xor dg(b/2-1 downto 0) );	
	
	-- RC 

	crdRegGen : process( rst, clk )
	begin		
		if ( rst = '0' ) then
			crd_out <= cr8_iv;
		elsif rising_edge( clk ) then
			if ( erf = '1' ) then
				crd_out <= cr8_iv;
			elsif ( er = '1' ) then
				crd_out <= crdp;
			end if;
		end if;
	end process;
	
	crdRoundInst: entity work.jh_rd(struct) 
		generic map ( bw => crw, cw => crkw ) 
		port map ( input => crd_out, cr => crkwzeros, output => crdp);
	-- ROUND

	roundInst 	: entity work.jh_rd(struct) 
		generic map ( bw => b, cw => crw  ) 
		port map ( input => rout, cr => crd_out, output => rd_out );
	
	dout <= hp(255 downto 0);
	
--	--debug

	 rin_m <= blk2wordmatrix_inv( rin );
	 rout_m <= blk2wordmatrix_inv( rout );
	 -- rd_out_m <= blk2wordmatrix_inv( rd_out(ux-1) );

	dg_m <= blk2wordmatrix_inv( dg );
	hp_m <= blk2wordmatrix_inv( hp );
	hm_m <= blk2wordmatrix_inv( hm );
--	crdo <= crd_out & zeros;

--	crd_out_m <= blk2wordmatrix_inv( crdo );

end struct;