------------------------------------------------------------ -- Copyright: 2011 George Mason University, Virginia USA -- http://www.iis.ee.ethz.ch/~sha3 ------------------------------------------------------------ -- ===================================================================== -- Copyright © 2010-2011 by Cryptographic Engineering Research Group (CERG), -- ECE Department, George Mason University -- Fairfax, VA, U.S.A. -- ===================================================================== library ieee; use ieee.std_logic_1164.all; use work.sha3_pkg.all; use work.sha3_jh_package.all; entity gmu_jh_top is port ( ClkxCI : in std_logic; -- Rising Edge Triggered Clock RstxRBI : in std_logic; -- Active-low, asynchronous Reset Signal ScanInxTI : in std_logic; ScanOutxTO : out std_logic; ScanEnxTI : in std_logic; InEnxSI : in std_logic; -- Input Enable FinBlockxSI : in std_logic; -- Final Block DataxDI : in std_logic_vector(511 downto 0); -- Input Data OutEnxSO : out std_logic; -- Output Enable PenUltCyclexSO : out std_logic; -- Penultimate Cycle DataxDO : out std_logic_vector(255 downto 0) -- Output Data ); end gmu_jh_top; architecture structure of gmu_jh_top is signal er, sf : std_logic; signal srdp : std_logic; signal erf : std_logic; begin control_gen : entity work.gmu_jh_control(beh) port map ( clk => ClkxCI, rst => RstxRBI, InEnxSI => InEnxSI, FinBlockxSI => FinBlockxSI, OutEnxSO => OutEnxSO, PenUltCyclexSO => PenUltCyclexSO, er => er, sf => sf, srdp => srdp, erf => erf ); datapath_gen : entity work.gmu_jh_datapath_otf(struct) port map ( clk => ClkxCI, rst => RstxRBI, din => DataxDI, dout => DataxDO, er => er, sf => sf, srdp => srdp, erf => erf ); end structure;