------------------------------------------------------------
-- Copyright: 2011 George Mason University, Virginia USA
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
-- =====================================================================

-- Copyright © 2010-2011 by Cryptographic Engineering Research Group (CERG),

-- ECE Department, George Mason University

-- Fairfax, VA, U.S.A.

-- =====================================================================


library ieee;
use ieee.std_logic_1164.all;	
use work.sha3_pkg.all;
use work.keccak_pkg.all;

entity gmu_keccak_top is
        port (
                ClkxCI         : in  std_logic;  -- Rising Edge Triggered Clock

                ScanInxTI      : in  std_logic;
                ScanOutxTO     : out std_logic;
                ScanEnxTI      : in  std_logic;
                RstxRBI        : in  std_logic;  -- Active-low, asynchronous Reset Signal

                InEnxSI        : in  std_logic;  -- Input Enable

                FinBlockxSI    : in  std_logic;  -- Final Block

                DataxDI        : in  std_logic_vector(1087 downto 0);  -- Input Data

                OutEnxSO       : out std_logic;  -- Output Enable

                PenUltCyclexSO : out std_logic;  -- Penultimate Cycle

                DataxDO        : out std_logic_vector(255 downto 0)  -- Output Data

        );         
end gmu_keccak_top;


architecture structure of gmu_keccak_top is 	 	
	signal sel_xor, sel_final, wr_state :std_logic;
	signal ld_rdctr, en_rdctr  : std_logic;	  
	signal rd_ctr : std_logic_vector(4 downto 0);
begin
	
	control_gen : entity work.gmu_keccak_control(struct)		
		port map (clk => ClkxCI, rst => RstxRBI, 
		InEnxSI => InEnxSI, FinBlockxSI => FinBlockxSI, OutEnxSO => OutEnxSO, PenUltCyclexSO => PenUltCyclexSO,
		sel_xor=>sel_xor, sel_final=>sel_final, wr_state=>wr_state, rd_ctr=>rd_ctr	);


	datapath_gen : entity work.gmu_keccak_datapath(struct)
		port map (
		clk => ClkxCI, rst => RstxRBI, din => DataxDI, dout => DataxDO,
		sel_xor=>sel_xor, sel_final=>sel_final, wr_state=>wr_state, rd_ctr=>rd_ctr		
		);	
   
end structure;